公开(公告)号：US20220093537A1

公开(公告)日：2022-03-24

申请号：US17031821

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN

IPC: H01L23/64 ,  H01L25/065 ,  H01L23/498 ,  H01F27/28 ,  H01F27/24 ,  H01F27/32

Abstract: Embodiments disclosed herein include electronic packages with embedded inductors. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment, the electronic package further comprises an inductor embedded in the package substrate, where the inductor comprises: a trace with a first end and a second end. In an embodiment, a magnetic material surrounds the trace between the first end and the second end. In an embodiment, a first via is connected to the first end, and a second via is connected to the second end.

公开(公告)号：US20210104475A1

公开(公告)日：2021-04-08

申请号：US16596328

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Krishna BHARATH ,  Clive HENDRICKS

IPC: H01L23/64 ,  H01F17/00 ,  H01F17/04 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments include an inductor, a method to form the inductor, and a semiconductor package. An inductor includes a plurality of plated-through-hole (PTH) vias in a substrate layer, and a plurality of magnetic interconnects with a plurality of openings in the substrate layer. The openings of the magnetic interconnects surround the PTH vias. The inductor also includes an insulating layer in the substrate layer, a first conductive layer over the PTH vias, magnetic interconnects, and insulating layer, and a second conductive layer below the PTH vias, magnetic interconnects, and insulating layer. The insulating layer surrounds the PTH vias and magnetic interconnects. The magnetic interconnects may have a thickness substantially equal to a thickness of the PTH vias. The magnetic interconnects may be shaped as hollow cylindrical magnetic cores with magnetic materials. The magnetic materials may include ferroelectric, conductive, or epoxy materials. The hollow cylindrical magnetic cores may be ferroelectric cores.

公开(公告)号：US20200373232A1

公开(公告)日：2020-11-26

申请号：US16993112

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/68

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20200051884A1

公开(公告)日：2020-02-13

申请号：US16059513

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Sameer SHEKHAR ,  Amit Kumar JAIN ,  Kaladhar RADHAKRISHNAN ,  Jonathan P. DOUGLAS ,  Chin Lee KUAN

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  G06F1/20

Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

公开(公告)号：US20190393165A1

公开(公告)日：2019-12-26

申请号：US16481031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Jaejin LEE ,  Hao-Han HSU ,  Chung-Hao J. CHEN ,  Dong-Ho HAN

IPC: H01L23/552 ,  H01L23/498 ,  H01L25/18 ,  H05K1/18 ,  H01L21/48

Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.