公开(公告)号：US10958589B2

公开(公告)日：2021-03-23

申请号：US15472384

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： James Dinan ,  Sayantan Sur ,  Mario Flajslik ,  Keith D. Underwood

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/919

Abstract: Technologies for offloaded management of communication are disclosed. In order to manage communication with information that may be available to applications in a compute device, the compute device may offload communication management to a host fabric interface using a credit management system. A credit limit is established, and each message to be sent is added to a queue with a corresponding number of credits required to send the message. The host fabric interface of the compute device may send out messages as credits become available and decrease the number of available credits based on the number of credits required to send a particular message. When an acknowledgement of receipt of a message is received, the number of credits required to send the corresponding message may be added back to an available credit pool.

公开(公告)号：US20190050274A1

公开(公告)日：2019-02-14

申请号：US15941984

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Timo Schneider ,  Keith D. Underwood

IPC: G06F9/52

Abstract: Technologies for synchronizing triggered operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command associated with a triggered operation that has been fired and determine whether the operation execution command includes an instruction to update a table entry of a table managed by the HFI. Additionally, the he HFI is configured to issue, in response to a determination that the operation execution command includes the instruction to update the table entry, a triggered list enable (TLE) operation and a triggered list disable (TLD) operation to a table manager of the HFI and disable a corresponding table entry in response to the TLD operation having been triggered, the identified table entry. The HFI is further configured to execute one or more command operations associated with the received operation execution command and re-enable, in response to the TLE operation having been triggered, the table entry. Other embodiments are described herein.

公开(公告)号：US20190042337A1

公开(公告)日：2019-02-07

申请号：US15859389

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Timo Schneider ,  Keith D. Underwood

IPC: G06F9/54 ,  G06F9/30

Abstract: Technologies for extending triggered operations include a host fabric interface (HFI) of a compute device configured to detect a triggering event associated with a counter, increment the counter, and determine whether a value of the counter matches a trigger threshold of a triggered operation in a triggered operation queue associated with the counter. The HFI is further configured to execute, one or more commands associated with the triggered operation upon determining that the value of the counter matches the trigger threshold, and determine, subsequent to the execution of the one or more commands, whether the triggered operation corresponds to a recurring triggered operation. The HFI is additionally configured to increment, in response to a determination that the triggered operation corresponds to a recurring triggered operation, the value of the trigger threshold by a threshold increment and re-insert the triggered operation into the triggered operation queue. Other embodiments are described herein.

公开(公告)号：US20180287954A1

公开(公告)日：2018-10-04

申请号：US15472384

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： James Dinan ,  Sayantan Sur ,  Mario Flajslik ,  Keith D. Underwood

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/919

Abstract: Technologies for offloaded management of communication are disclosed. In order to manage communication with information that may be available to applications in a compute device, the compute device may offload communication management to a host fabric interface using a credit management system. A credit limit is established, and each message to be sent is added to a queue with a corresponding number of credits required to send the message. The host fabric interface of the compute device may send out messages as credits become available and decrease the number of available credits based on the number of credits required to send a particular message. When an acknowledgement of receipt of a message is received, the number of credits required to send the corresponding message may be added back to an available credit pool.

公开(公告)号：US20180255477A1

公开(公告)日：2018-09-06

申请号：US15450651

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Eric R. Borch ,  Keith D. Underwood

IPC: H04W28/02 ,  H04W72/04

CPC classification number: H04W28/0289 ,  H04L49/00 ,  H04W72/0453 ,  Y02D70/00 ,  Y02D70/22 ,  Y02D70/26

Abstract: Technologies for link-bandwidth-aware routing are disclosed. In order to avoid congestion while still allowing link bandwidth to be decreased in order to save power, a network switch may select a port to send a packet over based on the present link bandwidth of the data links connected to the various output ports of the network switch. The network switch preferentially sends the packet over the minimal output port, or, if the minimal output port is congested, over one of the ports with the highest available link bandwidth. If the link bandwidth of the data link connected to the selected output port is not high enough, the network switch will automatically dynamically increase the link bandwidth of the data link as necessary.

公开(公告)号：US11409673B2

公开(公告)日：2022-08-09

申请号：US16275625

申请日：2019-02-14

Applicant: Intel Corporation

Inventor： Andrew Friedley ,  Sayantan Sur ,  Ravindra Babu Ganapathi ,  Travis Hamilton ,  Keith D. Underwood

IPC: G06F13/38 ,  G06F13/16 ,  G06F9/48 ,  G06F12/0802

Abstract: Examples include a method of managing storage for triggered operations. The method includes receiving a request to allocate a triggered operation; if there is a free triggered operation, allocating the free triggered operation; if there is no free triggered operation, recovering one or more fired triggered operations, freeing one or more of the recovered triggered operations, and allocating one of the freed triggered operations; configuring the allocated triggered operation; and storing the configured triggered operation in a cache on an input/output (I/O) device for subsequent asynchronous execution of the configured triggered operation.

公开(公告)号：US11194636B2

公开(公告)日：2021-12-07

申请号：US15941509

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  Keith D. Underwood ,  Timo Schneider ,  James Dinan

IPC: G06F9/54

Abstract: Technologies for generating triggered conditional events operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command message associated with a triggered operation that has been fired, process the received operation execution command message to extract and store argument information from the received operation execution command, and increment an event counter associated with the fired triggered operation. The HFI is further configured to perform a triggered compare-and-generate event (TCAGE) operation as a function of the extracted argument information, determine whether to generate a triggering event, generate the triggering event as a function of the performed TCAGE operation, insert the generated triggered event into a triggered operation queue, and update the value of the event counter. Other embodiments are described herein.

公开(公告)号：US11172016B2

公开(公告)日：2021-11-09

申请号：US15474833

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Karl P. Brummel ,  Charles A. Giefer ,  Nathan S. Miller ,  Keith D. Underwood

IPC: H04L29/08 ,  H04L12/801 ,  H04L12/823 ,  H04L12/851 ,  H04L12/807 ,  H04L12/835

Abstract: A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node. However, if transmitting the packet would violate the target node's concurrency limit, the circuitry would store the packet in a retransmit buffer of the computing device, where the retransmit buffer is to further store already transmitted packets flagged for retransmission. The circuitry would then transmit the packet from the retransmit buffer when transmitting the packet from the retransmit buffer would not violate the target node's concurrency limit.

公开(公告)号：US10693787B2

公开(公告)日：2020-06-23

申请号：US15686264

申请日：2017-08-25

Applicant: INTEL CORPORATION

Inventor： Timo Schneider ,  Keith D. Underwood ,  Mario Flajslik ,  Sayantan Sur ,  James Dinan

IPC: H04L12/801 ,  G06F9/48 ,  H04L12/935 ,  H04L12/803 ,  H04L29/08

Abstract: Techniques are disclosed to throttle bandwidth imbalanced data transfers. In some examples, an example computer-implemented method may include splitting a payload of a data transfer operation over a network fabric into multiple chunk get operations, starting the execution of a threshold number of the chunk get operations, and scheduling the remaining chunk get operations for subsequent execution. The method may also include executing a scheduled chunk get operation in response determining a completion of an executing chunk get operation. In some embodiments, the chunk get operations may be implemented as triggered operations.

公开(公告)号：US20190044883A1

公开(公告)日：2019-02-07

申请号：US15868110

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Janusz Piotr Jurski ,  Jonathan Eastep ,  Keith D. Underwood ,  Madhusudhan Rangarajan

IPC: H04L12/911 ,  H04L12/927 ,  H04L29/08

Abstract: In multi-processor systems, some large jobs are performed by dividing the job into multiple tasks, having each task executed in parallel by separate nodes, and combining or synchronizing the results into a final answer. When communications between nodes represent a significant portion of total performance, techniques may be used to monitor and balance communications between the nodes so that the tasks will be completed at approximately the same time, thereby accelerating the completion of the job and avoiding wasting time and power by having some processors sit idle while waiting for other processors to catch up. Multiple synchronization points may be set up between the start and finish of task execution, to that mid-course corrections may be made.