公开(公告)号：US20160174374A1

公开(公告)日：2016-06-16

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K1/11 ,  H01L21/48 ,  H05K3/40 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

Abstract translation: 公开了一种在衬底中包括垂直沟槽布线的互连拓扑。 在一个实施例中，互连包括具有包括第一接地平面层的多个层的衬底; 形成差分信号对的一对信号导体，所述一对信号导体中的每个导体具有第一部分和第二部分，所述第二部分从所述第一部分延伸到所述多个层中的至少一个层中，其中， 第二部分小于第一部分的宽度; 并且其中所述第一接地层仅为第一部分层，并且具有比所述第一部分层更靠近所述一对信号导体的第一空隙区域。

公开(公告)号：US20160174361A1

公开(公告)日：2016-06-16

申请号：US14567916

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Kuan-Yu Chen ,  Yun Ling ,  Mohd Muhaiyiddin Bin Abdullah ,  Jackson Chung Peng Kong ,  Chung-Hao Chen ,  Hao-Han Hsu ,  Xiang Li

IPC: H05K1/02 ,  H01P11/00 ,  H01P3/08

CPC classification number: H05K1/0242 ,  H01P3/026 ,  H01P3/18 ,  H01P11/003 ,  H05K1/0216 ,  H05K1/0245 ,  H05K3/4644

Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.

Abstract translation: 描述用于在电路板中路由信号迹线的技术。 根据所述技术的电子设备的示例包括包括多个导电层的电路板。 导电层包括信号层和参考平面。 信号层包括信号迹线，参考平面包括附加信号迹线。

公开(公告)号：US20160172793A1

公开(公告)日：2016-06-16

申请号：US14567767

申请日：2014-12-11

Applicant: INTEL CORPORATION

Inventor： Kuan-Yu Chen

IPC: H01R13/6592 ,  H01R43/16

CPC classification number: H01R13/6471 ,  H01R9/035 ,  H01R12/57

Abstract: Techniques for signal line connecting are described herein. An apparatus may include a first signal contact pad and a second signal contact pad adjacent to the first signal contact pad. The apparatus also includes a ground pad. The contact pads are disposed in an arrangement reducing inequality between unshielded lengths of a first signal line, a second signal line, and a drain line lines to be respectively connected to the first signal contact pad, the second signal contact pad, and the ground contact pad.

Abstract translation: 本文描述了用于信号线连接的技​​术。 装置可以包括第一信号接触焊盘和与第一信号接触焊盘相邻的第二信号接触焊盘。 该装置还包括接地垫。 接触焊盘以排列方式设置，从而减小第一信号线，第二信号线和漏极线之间的非屏蔽长度上的不等式，以分别连接到第一信号接触焊盘，第二信号接触焊盘和接地触头 垫。