公开(公告)号：US20160211619A1

公开(公告)日：2016-07-21

申请号：US14601403

申请日：2015-01-21

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Howard L Heck ,  Kuan-Yu Chen ,  Boon Ping Koh ,  Min Keen Tang ,  Kooi Chi Ooi

IPC: H01R13/648 ,  H01R24/66

CPC classification number: H01R13/6485 ,  H01R24/66 ,  H01R2107/00

Abstract: In one example an electronic device comprises a housing. A receptacle in the housing comprising an opening at a distal end to receive a plug and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly is coupled to a dedicated electrical discharge path. Other examples may be described.

Abstract translation: 在一个示例中，电子设备包括壳体。 壳体中的容器包括在远端处的开口，用于容纳插头和靠近插座中的开口定位的静电导体组件，其中静电导体组件耦合到专用放电路径。 可以描述其他示例。

公开(公告)号：US09755334B2

公开(公告)日：2017-09-05

申请号：US14750875

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Xiang Li ,  Yun Ling ,  Chung-Hao J. Chen ,  Hao-Han Hsu ,  Shyamjith Mohan ,  Kuan-Yu Chen

IPC: H01R12/00 ,  H01R12/70 ,  H01R13/6585 ,  H01R12/79 ,  H01R13/6592 ,  H01R12/77 ,  H01R12/59 ,  H01R12/88

CPC classification number: H01R12/7076 ,  H01R12/594 ,  H01R12/7011 ,  H01R12/774 ,  H01R12/775 ,  H01R12/79 ,  H01R12/88 ,  H01R13/6585 ,  H01R13/6592

Abstract: A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.

公开(公告)号：US20160181736A1

公开(公告)日：2016-06-23

申请号：US14573007

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Hao-Han Hsu ,  Kuan-Yu Chen ,  Xiang Li

IPC: H01R13/6594 ,  H01R43/20

CPC classification number: H01R13/6594 ,  H01R12/721 ,  H01R12/724 ,  H01R43/20

Abstract: An apparatus is described. The apparatus includes an add-on conductive attachment that includes a single piece of material. The add-on conductive attachment is to suppress radiation from a connector. The apparatus includes a plurality of ground pads, where at least one end-portion of the add-on conductive attachment is to couple with a ground pad of a printed circuit board (PCB) via at least one of the ground pads.

Abstract translation: 描述了一种装置。 该装置包括附加导电附件，其包括单片材料。 附加导电附件是为了抑制来自连接器的辐射。 该装置包括多个接地焊盘，其中附加导电附件的至少一个端部部分经由至少一个接地焊盘与印刷电路板（PCB）的接地焊盘耦合。

公开(公告)号：US20160380386A1

公开(公告)日：2016-12-29

申请号：US14750846

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Kuan-Yu Chen ,  Bok Eng Cheah ,  Boon Ping Koh ,  Min Keen Tang ,  Howard L. Heck ,  Kooi Chi Ooi

IPC: H01R13/648 ,  H01R13/42

CPC classification number: H01R13/6485 ,  H05K9/0067

Abstract: In one example an electronic device comprises a housing, a receptacle in the housing comprising an opening at a distal end to receive a plug, a data connector positioned in the receptacle to provide a communication connection, and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly comprises a dedicated discharge path and a conductive pin mounted on a retention latch and moveable between a first position in which the conductive pin is in electrical contact with the data connector and a second position in which the conductive pin is not in electrical contact with the data connector. Other examples may be described.

Abstract translation: 在一个示例中，电子设备包括壳体，壳体中的插座，包括在远端处的接收插头的开口，位于插座中的数据连接器以提供通信连接，以及定位在开口附近的静电导体组件 插座，其中所述静电导体组件包括专用放电路径和安装在保持闩锁上的导电针，并且可在所述导电针与所述数据连接器电接触的第一位置和在所述第二位置之间移动的第二位置， 不与数据连接器电接触。 可以描述其他示例。

公开(公告)号：US09496656B2

公开(公告)日：2016-11-15

申请号：US14573007

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Hao-Han Hsu ,  Kuan-Yu Chen ,  Xiang Li

IPC: H01R13/6594 ,  H01R13/658 ,  H01R43/20

CPC classification number: H01R13/6594 ,  H01R12/721 ,  H01R12/724 ,  H01R43/20

Abstract: An apparatus is described. The apparatus includes an add-on conductive attachment that includes a single piece of material. The add-on conductive attachment is to suppress radiation from a connector. The apparatus includes a plurality of ground pads, where at least one end-portion of the add-on conductive attachment is to couple with a ground pad of a printed circuit board (PCB) via at least one of the ground pads.

Abstract translation: 描述了一种装置。 该装置包括附加导电附件，其包括单片材料。 附加导电附件是为了抑制来自连接器的辐射。 该装置包括多个接地焊盘，其中附加导电附件的至少一个端部部分经由至少一个接地焊盘与印刷电路板（PCB）的接地焊盘耦合。

公开(公告)号：US09326380B2

公开(公告)日：2016-04-26

申请号：US13727701

申请日：2012-12-27

Applicant: INTEL CORPORATION

Inventor： Kuan-Yu Chen ,  Howard L. Heck

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H01R12/57 ,  H05K1/02 ,  H01R12/58

CPC classification number: H05K1/11 ,  H01R12/57 ,  H01R12/58 ,  H05K1/025 ,  H05K1/0269 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/115 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/10189 ,  H05K2201/10659 ,  H05K2201/2045 ,  H05K2203/163 ,  Y10T29/49124

Abstract: A universal serial bus hybrid footprint design is described herein. The design includes an outer row of one or more surface mount technology (SMT) contacts and an inner row of one or more printed through holes (PTH). The hybrid footprint design enables a data through put of at least 10 Gbps.

Abstract translation: 本文描述了通用串行总线混合覆盖设计。 该设计包括一排或多个表面贴装技术（SMT）触点和一列或多个印刷通孔（PTH）的内排。 混合足迹设计能够通过至少10 Gbps的数据进行数据传输。

公开(公告)号：US20250086370A1

公开(公告)日：2025-03-13

申请号：US18958896

申请日：2024-11-25

Applicant: Intel Corporation

Inventor： Kuan-Yu Chen ,  Michael Wilmer Leddige ,  Diego Mauricio Cortes Hernandez ,  John Sharpe

IPC: G06F30/392 ,  G06F30/27 ,  G06F30/3947 ,  G06F115/12 ,  G06F119/10

Abstract: An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify crosstalk between a first signal via and a second signal via on a printed circuit board (PCB) layout, determine an area for placement of a ground via between the first signal via and the second signal via, and classify one or more regions of the PCB layout into at least one of a protective area or a non-protective area based on the area for placement of the ground via.

公开(公告)号：US10079158B2

公开(公告)日：2018-09-18

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K7/00 ,  H01P3/08 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H05K1/00 ,  H05K1/11 ,  H01P3/00 ,  H01P3/02 ,  H01P5/02 ,  H05K1/02 ,  H01P3/04

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

公开(公告)号：US09596749B2

公开(公告)日：2017-03-14

申请号：US14567916

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Kuan-Yu Chen ,  Yun Ling ,  Mohd Muhaiyiddin Bin Abdullah ,  Jackson Chung Peng Kong ,  Chung-Hao Chen ,  Hao-Han Hsu ,  Xiang Li

IPC: H05K1/02 ,  H01P3/18 ,  H01P3/02 ,  H05K3/46 ,  H01P11/00

CPC classification number: H05K1/0242 ,  H01P3/026 ,  H01P3/18 ,  H01P11/003 ,  H05K1/0216 ,  H05K1/0245 ,  H05K3/4644

Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.

Abstract translation: 描述用于在电路板中路由信号迹线的技术。 根据所述技术的电子设备的示例包括包括多个导电层的电路板。 导电层包括信号层和参考平面。 信号层包括信号迹线，参考平面包括附加信号迹线。

公开(公告)号：US09484680B2

公开(公告)日：2016-11-01

申请号：US13915872

申请日：2013-06-12

Applicant: Intel Corporation

Inventor： Pujitha Davuluri ,  Chung-Hao J. Chen ,  Kuan-Yu Chen

IPC: H01R13/659 ,  H01R13/6597 ,  H01R13/6582 ,  H01R13/6594

CPC classification number: H01R13/6597 ,  H01R13/6582 ,  H01R13/6594

Abstract: An apparatus is described herein. The apparatus includes a receptacle to receive a plug to couple a peripheral device to a computing device. The apparatus includes a ground contact of a printed circuit board of the computing device. The apparatus includes a shield communicatively coupled to the ground contact, wherein the shield is to reduce radio frequency interference (RFI) from an interface between the plug and the receptacle.

Abstract translation: 这里描述了一种装置。 该装置包括用于接收插头以将外围设备耦合到计算设备的插座。 该装置包括计算装置的印刷电路板的接地触点。 该装置包括通信地耦合到接地触点的屏蔽，其中屏蔽件用于减少插头和插座之间的接口的射频干扰（RFI）。