公开(公告)号：US10747640B2

公开(公告)日：2020-08-18

申请号：US15635270

申请日：2017-06-28

Applicant: INTEL CORPORATION

Inventor： Ananth S. Narayan ,  Lukasz Grzymkowski ,  Mrittika Ganguli ,  Mariusz Oriol

IPC: G06F11/34 ,  G06F9/38 ,  H04Q9/04 ,  H03K19/0175 ,  G06F9/50 ,  H04Q9/00 ,  G06F30/327 ,  G06F9/48

Abstract: Techniques and apparatus for managing a distributed computing environment using event digests are described. In one embodiment, for example, an apparatus may include at least one memory, and logic for a system manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a workload to schedule, access an event digest associated with a plurality of compute hosts, the event digest comprising event digest values determined using out-of-band information, determine metrics from the event digest, generate at least one host weight for at least a portion of the plurality of compute hosts based on the metrics, identify at least one candidate host from the portion of the plurality of compute hosts based on the at least one host weight, and schedule the workload on the at least one candidate host. Other embodiments are described and claimed.

公开(公告)号：US10404676B2

公开(公告)日：2019-09-03

申请号：US15084377

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Justin J. Song ,  Devadatta V. Bodas ,  Muralidhar Rajappa ,  Andy Hoffman ,  Mariusz Oriol ,  Gopal R. Mundada

IPC: H04L29/06 ,  G06F1/3203 ,  G06F21/55 ,  H04L12/24

Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.

公开(公告)号：US20180372551A1

公开(公告)日：2018-12-27

申请号：US15629625

申请日：2017-06-21

Applicant: Intel Corporation

Inventor： Janusz P. Jurski ,  Tozer J. Bandorawalla ,  Ramkumar Nagappan ,  Mariusz Oriol ,  Piotr Sawicki ,  Robin A. Steinbrecher ,  Shankar Krishnan

IPC: G01K3/08 ,  F24F11/00

Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.

公开(公告)号：US10073742B2

公开(公告)日：2018-09-11

申请号：US15178142

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Robert C. Swanson ,  Mariusz Oriol ,  Janusz Jurski ,  Piotr Sawicki ,  Robert W. Cone ,  William J. O'Sullivan ,  Mariusz Stepka ,  Babak Nikjou ,  Madhusudhan Rangarajan ,  Pawel Szymanski ,  Piotr Kwidzinski ,  Robert Bahnsen ,  Mallik Bulusu

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/20 ,  G06F9/50 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F11/142 ,  G06F1/3296 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/5088 ,  G06F11/14 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2033 ,  G06F11/2035 ,  G06F11/2043 ,  G06F2201/805 ,  G06F2201/85

Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.

公开(公告)号：US09891686B2

公开(公告)日：2018-02-13

申请号：US14038347

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Janusz Jurski ,  Robert Swanson ,  Anil Kumar ,  Mariusz Oriol ,  Waldemar Piotrewicz

IPC: G06F1/30 ,  G06F1/32

CPC classification number: G06F1/30 ,  G06F1/329 ,  Y02D10/24

Abstract: An apparatus and system for throttling I/O devices in a computer system is provided. In an example, a method for throttling device power demand during critical power events. The method includes detecting a critical power event and issuing a signal to system devices to defer optional transactions during the critical power event.

公开(公告)号：US09367406B2

公开(公告)日：2016-06-14

申请号：US14125516

申请日：2013-08-14

Applicant: Intel Corporation

Inventor： Robert C. Swanson ,  Mariusz Oriol ,  Janusz Jurski ,  Piotr Sawicki ,  Robert W. Cone ,  William J. O'Sullivan ,  Mariusz Stepka ,  Babak Nikjou ,  Madhusudhan Rangarajan ,  Pawel Szymanski ,  Piotr Kwidzinski ,  Robert Bahnsen ,  Mallik Bulusu

IPC: G06F11/00 ,  G06F11/20 ,  G06F9/50 ,  G06F11/14

CPC classification number: G06F11/142 ,  G06F1/3296 ,  G06F9/4881 ,  G06F9/5027 ,  G06F9/5088 ,  G06F11/14 ,  G06F11/2023 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2033 ,  G06F11/2035 ,  G06F11/2043 ,  G06F2201/805 ,  G06F2201/85

Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.

Abstract translation: 介绍了为微服务器和集群系统级芯片（SoC）部署提供可管理性冗余的技术。 可配置的多处理器装置可以包括多个集成电路（IC）块，其中每个IC块包括执行一个或多个可分配任务功能的任务块和用于执行相对于IC块的管理功能的管理块。 每个任务块和每个管理块可以包括一个或多个指令处理器和对应的存储器。 每个IC块可以是可控制的，以执行一个或多个其它IC块的功能。 IC块可以经由管理通信基础设施相互通信，管理通信基础设施可以包括从每个管理块到每个其他管理块的通信路径。 通过管理通信基础设施，管理块可以跨越管理块对之间的通信路径。