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公开(公告)号：US10739729B2
公开(公告)日：2020-08-11
申请号：US16242953
申请日：2019-01-08
Applicant: Intel Corporation
Inventor： Tarun Mahajan , Dheeraj Shetty , Ramnarayanan Muthukaruppan
IPC: H03M1/50 , G04F10/00 , G05F1/56 , G06F1/12 , G06F1/06 , H03M1/00 , H03M1/12 , H03M1/74 , H03L7/089 , H03L7/081 , H03L7/10
Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.
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公开(公告)号：US09831863B2
公开(公告)日：2017-11-28
申请号：US15350404
申请日：2016-11-14
Applicant: Intel Corporation
Inventor： Santosh Nene , Tarun Mahajan , Venkataraman Srinivasan , Ramnarayanan Muthukaruppan
CPC classification number: H03K5/1565 , G01R19/25 , G01R19/2506 , H02M1/088 , H02M3/158 , H02M2001/0009 , H02M2001/0022 , H03K3/017
Abstract: Some embodiments include apparatus and methods having a node to provide a signal, and a control unit arranged to control a value of an output voltage at an output node on an output path based on a duty cycle of the signal and a value of an input voltage. The control unit can also be arranged to cause a change in a resistance on the output path in order to determine a value of a current on the output path based at least on the change in the resistance.
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公开(公告)号：US09766678B2
公开(公告)日：2017-09-19
申请号：US13758897
申请日：2013-02-04
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
CPC classification number: G06F1/32 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/152 , Y02D10/172
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US09496852B2
公开(公告)日：2016-11-15
申请号：US14560073
申请日：2014-12-04
Applicant: Intel Corporation
Inventor： Santosh Nene , Tarun Mahajan , Venkataraman Srinivasan , Ramnarayanan Muthukaruppan
CPC classification number: H03K5/1565 , G01R19/25 , G01R19/2506 , H02M1/088 , H02M3/158 , H02M2001/0009 , H02M2001/0022 , H03K3/017
Abstract: Some embodiments include apparatus and methods having a node to provide a signal, and a control unit arranged to control a value of an output voltage at an output node on an output path based on a duty cycle of the signal and a value of an input voltage. The control unit can also be arranged to cause a change in a resistance on the output path in order to determine a value of a current on the output path based at least on the change in the resistance.
Abstract translation: 一些实施例包括具有提供信号的节点的装置和方法，以及控制单元，其被配置为基于信号的占空比和输入电压的值来控制输出路径上的输出节点处的输出电压的值 。 控制单元还可以被布置成使得输出路径上的电阻发生变化，以便至少基于电阻的变化确定输出路径上的电流值。
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公开(公告)号：US11068006B2
公开(公告)日：2021-07-20
申请号：US16377042
申请日：2019-04-05
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Chepuri
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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Patent Agency Ranking
公开(公告)号：US11048283B2
公开(公告)日：2021-06-29
申请号：US16798741
申请日：2020-02-24
Applicant: Intel Corporation
Inventor： Tarun Mahajan , Ramnarayanan Muthukaruppan , Rajesh Sidana , Srinath B. Pai
Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a control circuitry to generate error information based on a value of the feedback voltage generated from an output voltage, generate output information to control a power switching unit based on the error information provided to a forward path in the control circuitry, and adjust a gain of the forward path based on a gain factor computed based at least in part on a first value of the output information in order to cause the output information to have a second value. The control circuitry also computes a value of correction information when the output voltage is within a target value range, and adjusts the control information, based on the correction information, when the output voltage is outside the target value range.
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公开(公告)号：US20200264645A1
公开(公告)日：2020-08-20
申请号：US16798741
申请日：2020-02-24
Applicant: Intel Corporation
Inventor： Tarun Mahajan , Ramnarayanan Muthukaruppan , Rajesh Sidana , Srinath B. Pai
IPC: G05F1/575
Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a control circuitry to generate error information based on a value of the feedback voltage generated from an output voltage, generate output information to control a power switching unit based on the error information provided to a forward path in the control circuitry, and adjust a gain of the forward path based on a gain factor computed based at least in part on a first value of the output information in order to cause the output information to have a second value. The control circuitry also computes a value of correction information when the output voltage is within a target value range, and adjusts the control information, based on the correction information, when the output voltage is outside the target value range.
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公开(公告)号：US20190235557A1
公开(公告)日：2019-08-01
申请号：US16377042
申请日：2019-04-05
Applicant: Intel Corporation
Inventor： Rupak Ghayal , Pradipta Patra , Ramnarayanan Muthukaruppan , Raghu Chepuri
IPC: G05F3/02
CPC classification number: G05F3/02
Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
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公开(公告)号：US10185382B2
公开(公告)日：2019-01-22
申请号：US15292067
申请日：2016-10-12
Applicant: Intel Corporation
Inventor： Ramnarayanan Muthukaruppan , Harish K. Krishnamurthy , Mohit Verma , Pradipta Patra , Uday Bhaskar Kadali
Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
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公开(公告)号：US10175655B2
公开(公告)日：2019-01-08
申请号：US15462732
申请日：2017-03-17
Applicant: Intel Corporation
Inventor： Tarun Mahajan , Dheeraj Shetty , Ramnarayanan Muthukaruppan
Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.
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