公开(公告)号：US20220012016A1

公开(公告)日：2022-01-13

申请号：US17485179

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G06F7/544 ,  G06F7/523 ,  G06N3/04 ,  H03M1/78 ,  H03M1/80

Abstract: Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

公开(公告)号：US20240045723A1

公开(公告)日：2024-02-08

申请号：US18477816

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Renzhi Liu ,  Henchen Wang ,  Brent Carlton

IPC: G06F9/50 ,  G11C7/10

CPC classification number: G06F9/5033 ,  G06F9/5016 ,  G11C7/1012

Abstract: Systems, apparatuses and methods include technology that executes, with a compute-in-memory (CiM) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (CnM) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (CoM) element, third computations based on third data associated with the workload. The technology further receives, with a multiplexer, processed data from a first element of the CiM element, the CnM element and the CoM element, and provides, with the multiplexer, the processed data to a second element of the CiM element, the CnM element and the CoM element.

公开(公告)号：US20230289066A1

公开(公告)日：2023-09-14

申请号：US18187950

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F3/06 ,  G06N3/0464 ,  G06F7/544

CPC classification number: G06F3/0613 ,  G06N3/0464 ,  G06F3/0659 ,  G06F3/0673 ,  G06F7/5443

Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.

公开(公告)号：US20230229504A1

公开(公告)日：2023-07-20

申请号：US17937248

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F9/50 ,  G06F7/544 ,  H03M1/18

CPC classification number: G06F9/5027 ,  G06F7/5443 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

公开(公告)号：US20200314751A1

公开(公告)日：2020-10-01

申请号：US16369953

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Asma Beevi Kuriparambil Thekkumpate ,  Brent Carlton

IPC: H04W52/02

Abstract: A communication device can include a receiver frontend and a wake-up receiver (WUR) frontend. The receiver frontend can have a radio frequency (RF) interface configured to couple to an antenna and a baseband interface configured to couple to a baseband component. The WUR frontend can be selectively coupled to the receiver frontend (e.g. between the RF interface and the baseband interface). The WUR frontend may monitor a communication channel and control the receiver frontend to adjust its operating mode (e.g. waking the receiver frontend from a sleep mode) based on the monitoring. The WUR frontend may have a lower power consumption than the receiver frontend. The WUR frontend and the receiver frontend may share the same impedance matching network and/or the RF interface.

公开(公告)号：US12196807B2

公开(公告)日：2025-01-14

申请号：US17133659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Renzhi Liu ,  Jong-Ru Guo ,  Kenneth P. Foust ,  Jason A. Mix ,  Kai Xiao ,  Zuoguo Wu ,  Daqiao Du

IPC: G01R31/302 ,  G01R31/28 ,  G01R31/303 ,  H01P3/08 ,  H01Q9/16 ,  H04B5/48

Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

公开(公告)号：US20240396568A1

公开(公告)日：2024-11-28

申请号：US18792714

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Brent Carlton

IPC: H03M1/14 ,  G06F7/544 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for technology including a digital to analog conversion (DAC) stage to generate analog input activation signals, a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage, an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results, and analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage, and a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.

公开(公告)号：US12095712B2

公开(公告)日：2024-09-17

申请号：US17131862

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Brent R. Carlton ,  Asma Beevi Kuriparambil Thekkumpate ,  Renzhi Liu ,  Rinkle Jain

IPC: H04L5/14 ,  H04B1/44 ,  H04L25/02 ,  H04L25/03 ,  H04W52/02 ,  H04W74/00 ,  H04W74/0808

CPC classification number: H04L5/1461 ,  H04B1/44 ,  H04L5/143 ,  H04L25/03834 ,  H04W52/0235 ,  H04W74/008

Abstract: A transceiver may include a transmitter device, a receiver device, a secondary receiver device, and switching elements. The transmitter device may provide a transmit control signal on first and second channels. The receiver device may receive a receive control signal on the first and second channels. The secondary receiver device may monitor occupation of the first and second channels without decoding at least a portion of control signals concurrent with the receiver device receiving the receive control signal. The switching elements may control when the transmitter device provides the transmit control signal to one of and is electrically isolated from first and second antennas, the receiver device receives the receive control signal from one of and is electrically isolated from the first and second antennas, and the secondary receiver device monitors occupation of one of the first and second channels and is electrically isolated from the first and second antennas.

公开(公告)号：US20240113725A1

公开(公告)日：2024-04-04

申请号：US18539957

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: H03M1/46 ,  G11C7/16

CPC classification number: H03M1/466 ,  G11C7/16 ,  H03M1/462

Abstract: Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.

公开(公告)号：US20230366923A1

公开(公告)日：2023-11-16

申请号：US18358458

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Sarah Shahraini ,  Mohamed Abdelmoneum ,  Richard Dorrance ,  Renzhi Liu ,  Eduardo Alban

IPC: G01R31/28 ,  G06N20/00

CPC classification number: G01R31/2874 ,  G01R31/2879 ,  G06N20/00

Abstract: Systems, apparatuses and methods may provide for chip technology including a memory structure having stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings, and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip.