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    Heterogeneous interconnect having linear and non-linear conductive pathways
    1.
    发明授权
    Heterogeneous interconnect having linear and non-linear conductive pathways 有权

    公开(公告)号：US10157822B1

    公开(公告)日：2018-12-18

    申请号：US15721691

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Zhen Zhou ,  Tae Young Yang ,  Guosong Lin ,  Ling Zheng ,  Daqiao Du

    IPC: H01L23/498 ,  H01L23/60 ,  H01L23/522

    Abstract: Electrical interconnects having a non-linear conductive pathway, and related apparatuses and methods, are disclosed herein. In some embodiments, an electrical interconnect may include a non-linear conductive pathway electrically coupling top and bottom conductive portions. In some embodiments, an electrical interconnect may include a non-linear conductive pathway that propagates an electrical signal generating electromagnetic fields with an electrical field orthogonal to the direction of electromagnetic-wave propagation. In some embodiments, an electrical interconnect may include a non-linear conductive pathway portion and a linear conductive pathway portion. Also disclosed are connectors including an electrical interconnect having a non-linear conductive pathway. In some embodiments, a connector may include a first electrical interconnect having a non-linear conductive pathway generating first electromagnetic fields; and second electrical interconnect having a linear conductive pathway generating second electromagnetic fields that are orthogonal to the first electromagnetic fields.

    ELECTRICAL INTERCONNECT WITH IMPROVED IMPEDANCE
    2.
    发明申请
    ELECTRICAL INTERCONNECT WITH IMPROVED IMPEDANCE 有权

    公开(公告)号：US20220013944A1

    公开(公告)日：2022-01-13

    申请号：US17484865

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： Daqiao Du ,  Zhen Zhou ,  Ismael Franco Núñez ,  Gordon P. Melz

    IPC: H01R13/05 ,  H01R13/11 ,  H01R43/00 ,  H01R12/71

    Abstract: An apparatus comprising an interconnect comprising a conductive core; a first conductive layer connected to the conductive core and extending parallel to the conductive core towards a first end of the conductive core; a second conductive layer connected to the conductive core and extending parallel to the conductive core towards a second end of the conductive core; a first non-conductive layer between the conductive core and the first conductive layer; and a second non-conductive layer between the first conductive layer and the second conductive layer.

    PHASE HETEROGENEOUS INTERCONNECTS FOR CROSSTALK REDUCTION
    3.
    发明申请
    PHASE HETEROGENEOUS INTERCONNECTS FOR CROSSTALK REDUCTION 有权

    公开(公告)号：US20220338344A1

    公开(公告)日：2022-10-20

    申请号：US17855680

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Zhen Zhou ,  Gordon Melz ,  Daqiao Du ,  Ismael Franco ,  Jason Mix

    IPC: H05K1/02 ,  H05K1/11

    Abstract: Methods and apparatus relating to phase heterogeneous interconnects for crosstalk reduction are described. In one embodiment, an interconnect includes a plurality of links. A first set of links from the plurality of links communicates signals and a second set of links from the plurality of links provides a return path. The interconnect also includes one or more links from the first set of links that include one or more structures with a larger diameter than a minimum diameter of the one or more links. The larger diameter modifies an inductance or capacitance of the one or more links to provide a heterogenous phase delay amongst the plurality of links. Other embodiments are also claimed and disclosed.

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