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公开(公告)号：US11749606B2
公开(公告)日：2023-09-05
申请号：US17371293
申请日：2021-07-09
Applicant: Intel Corporation
Inventor： Amit Kumar Jain , Sameer Shekhar , Chin Lee Kuan , Kevin Joseph Doran , Dong-Ho Han
IPC: H01L23/538 , H01L49/02 , H01L23/00
CPC classification number: H01L23/5381 , H01L23/5383 , H01L28/20 , H01L28/40 , H01L23/5384 , H01L24/16 , H01L2224/16225
Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
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12.发明授权公开(公告)号：US11437294B2
公开(公告)日：2022-09-06
申请号：US16059513
申请日：2018-08-09
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit Kumar Jain , Kaladhar Radhakrishnan , Jonathan P. Douglas , Chin Lee Kuan
IPC: H01L23/367 , H01L23/498 , H01L23/522 , H01L23/00 , G06F1/20
Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.
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公开(公告)号：US11380623B2
公开(公告)日：2022-07-05
申请号：US15939162
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Chin Lee Kuan , Amit Kumar Jain
IPC: H01L23/552 , H01L23/00 , H01L23/498 , H01F27/36 , H05K9/00
Abstract: Embodiments herein relate to a package having a substrate with a core layer with a plurality of conductors coupling a first side of the core layer with a second side of the core layer, and a shield within the core layer that separates a first conductor of the plurality of conductors from a second conductor of the plurality of conductors where the shield is to reduce electromagnetic interference received by the second conductor that is generated by the first conductor. Embodiments may also be related to a package having a substrate with a through hole via through the substrate, where an EMI protective material is applied to a surface of the substrate that forms the via to shield an inner portion of the via.
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公开(公告)号：US20190304915A1
公开(公告)日：2019-10-03
申请号：US16446920
申请日：2019-06-20
Applicant: Intel Corporation
Inventor： Amit Kumar Jain , Sameer Shekhar , Chin Lee Kuan , Kevin Joseph Doran , Dong-Ho Han
IPC: H01L23/538 , H01L49/02
Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
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公开(公告)号：US20180375438A1
公开(公告)日：2018-12-27
申请号：US15631996
申请日：2017-06-23
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Alexander Waizman , Michael Zelikson , Chin Lee Kuan
Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20180364775A1
公开(公告)日：2018-12-20
申请号：US15627159
申请日：2017-06-19
Applicant: Intel Corporation
Inventor： Amit K. Jain , Chin Lee Kuan , Sameer Shekhar
IPC: G06F1/26
Abstract: Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.
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公开(公告)号：US20210208656A1
公开(公告)日：2021-07-08
申请号：US16735563
申请日：2020-01-06
Applicant: Intel Corporation
Inventor： Alexander Uan-Zo-Li , Eugene Gorbatov , Harish Krishnamurthy , Alexander Lyakhov , Patrick Leung , Stephen Gunther , Arik Gihon , Khondker Ahmed , Philip Lehwalder , Sameer Shekhar , Vishram Pandit , Nimrod Angel , Michael Zelikson
Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
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公开(公告)号：US10972001B2
公开(公告)日：2021-04-06
申请号：US16102203
申请日：2018-08-13
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Ravi Sankar Vunnam
Abstract: Some embodiments include apparatuses having a switching circuit included in a buck converter; an output node; an inductor including a first portion having a first terminal coupled to the switching circuit, a second portion having a second terminal coupled to the output node, and a third terminal between the first and second portions; and a capacitor coupled to the second terminal, the second terminal to couple to a first additional capacitor, and the third terminal to couple to a second additional capacitor.
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公开(公告)号：US10719109B2
公开(公告)日：2020-07-21
申请号：US15627159
申请日：2017-06-19
Applicant: Intel Corporation
Inventor： Amit K. Jain , Chin Lee Kuan , Sameer Shekhar
IPC: G06F1/26
Abstract: Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.
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公开(公告)号：US20200052583A1
公开(公告)日：2020-02-13
申请号：US16102203
申请日：2018-08-13
Applicant: Intel Corporation
Inventor： Sameer Shekhar , Amit K. Jain , Ravi Sankar Vunnam
Abstract: Some embodiments include apparatuses having a switching circuit included in a buck converter; an output node; an inductor including a first portion having a first terminal coupled to the switching circuit, a second portion having a second terminal coupled to the output node, and a third terminal between the first and second portions; and a capacitor coupled to the second terminal, the second terminal to couple to a first additional capacitor, and the third terminal to couple to a second additional capacitor.
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