公开(公告)号：US11764187B2

公开(公告)日：2023-09-19

申请号：US16641241

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US20230268291A1

公开(公告)日：2023-08-24

申请号：US17679189

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Stephan Stoeckl ,  Sonja Koller ,  Wolfgang Molzer ,  Thomas Wagner ,  Pouya Talebbeydokhti

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/552

Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.

公开(公告)号：US20230268286A1

公开(公告)日：2023-08-24

申请号：US17679185

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Stephan Stoeckl ,  Thomas Wagner ,  Sonja Koller ,  Wolfgang Molzer ,  Pouya Talebbeydokhti

IPC: H01L23/552 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments of a microelectronic assembly comprise a package substrate, including: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer, and the third layer comprises a second material different from the first material.

公开(公告)号：US20220294115A1

公开(公告)日：2022-09-15

申请号：US17831151

申请日：2022-06-02

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoecki ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US11177220B2

公开(公告)日：2021-11-16

申请号：US16490521

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Andreas Wolter ,  Bernd Waidhas ,  Thomas Wagner

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Electronics devices, having vertical and lateral redistribution interconnects, are disclosed. An electronics device comprises an electronics component (e.g., die, substrate, integrated device, etc.), a die(s), and a separately formed redistribution connection layer electrically coupling the die(s) to the electronics component. The redistribution connection layer comprises dielectric layers on either side of at least one redistribution layer. The dielectric layers comprise openings that expose contact pads of the at least one redistribution layer for electrically coupling die(s) and components to each other via the redistribution connection layer. The redistribution connection layer is flexible and wrap/folded around side edges of die(s) to minimize vertical vias. Various devices and associated processes are provided.

公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20240364002A1

公开(公告)日：2024-10-31

申请号：US18139206

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/50 ,  H01Q1/2283 ,  H01Q9/045

Abstract: An antenna device includes integrated polymer nanocomposite (PNC) devices coupling an antenna on a substrate to both ground and signal terminals. The PNC devices may include PNC material between two electrodes. The PNC devices may be integrated into the antenna device with the substrate including at least one electrode of each of the PNC devices. One PNC device may convey a signal to or from the antenna, e.g., between the antenna and a signal terminal. Another PNC device may convey an electrostatic discharge (ESD) pulse to a ground terminal. The antenna device may include or be coupled to an integrated circuit (IC) die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US20230197615A1

公开(公告)日：2023-06-22

申请号：US17557134

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Peter Baumgartner ,  Bernd Waidhas ,  Wolfgang Molzer ,  Klaus Herold ,  Joachim Singer ,  Michael Langenbuch ,  Thomas Wagner

IPC: H01L23/528 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/645 ,  H01L23/5226

Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

公开(公告)号：US20230187353A1

公开(公告)日：2023-06-15

申请号：US17552010

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Martin Ostermayr ,  Klaus Herold ,  Joachim Singer ,  Thomas Wagner

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: Signal routing using structures based on buried power rails (BPRs) is described. An example IC device includes a support structure, a plurality of IC components provided over the support structure, and first and second electrically conductive structures having respective portions that are buried in the support structure, such structures referred to as “buried signal rails” (BSRs). The first BSR may be electrically coupled to a terminal of one of the plurality of IC components, the second BSR may be electrically coupled to a terminal of another one of the plurality of IC components, and the IC device may further include a bridge interconnect embedded within the support structure, the bridge interconnect having a first end in contact with the first BSR and a second end in contact with the second BSR. Implementing BSRs in IC devices may allow significantly increasing standard cell library density and provide geometry-free signal routing.

公开(公告)号：US11508637B2

公开(公告)日：2022-11-22

申请号：US16855418

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.