公开(公告)号：US09411725B2

公开(公告)日：2016-08-09

申请号：US13993620

申请日：2012-03-22

Applicant: Iosif Gasparakis ,  Peter P. Waskiewicz, Jr.

Inventor： Iosif Gasparakis ,  Peter P. Waskiewicz, Jr.

IPC: G06F12/08 ,  G06F9/50

CPC classification number: G06F12/0802 ,  G06F9/5016 ,  G06F2209/5014

Abstract: Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.

Abstract translation: 描述了用于直接I / O的缓存的应用保留使用的介质，方法和系统的实施例。 一种使用应用预留高速缓存的方法可以包括：由多个核心中的一个核心执行的应用程序使用多个级别的高速缓存中的一个级别的第一部分， 并且由多个核心中的一个核心将与应用程序相关联的数据从计算设备的输入/输出（I / O）设备直接传送到高速缓存的多个级别之一的第一部分。 可以描述和要求保护其他实施例。

公开(公告)号：US20140254594A1

公开(公告)日：2014-09-11

申请号：US13785693

申请日：2013-03-05

Applicant: Iosif Gasparakis ,  Peter P. Waskiewicz ,  Patrick Connor

Inventor： Iosif Gasparakis ,  Peter P. Waskiewicz ,  Patrick Connor

IPC: H04L12/56

CPC classification number: H04L45/74 ,  H04L47/50 ,  H04L61/6022 ,  H04L69/12 ,  H04L69/324

Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.

Abstract translation: 在网络接口控制器（NIC）流切换中实现的方法，设备和系统。 切换操作通过诸如NIC的设备中的基于硬件的转发机制以不使用计算机系统处理器资源的方式实现，并且对由这样的计算机系统托管的操作系统是透明的。 转发机制被配置为在与可能在同一NIC或单独NIC上的不同NIC端口相关联的接收（Rx）和发送（Tx）队列之间移动或复制媒体访问控制（MAC）帧数据。 基于硬件的交换操作通过存储器操作来影响NIC端口之间的MAC帧的转发，从而减少与分组处理相关联的外部网络流量，内部互连流量和处理器工作量。

公开(公告)号：US20130343229A1

公开(公告)日：2013-12-26

申请号：US13532971

申请日：2012-06-26

Applicant: Iosif Gasparakis

Inventor： Iosif Gasparakis

IPC: H04L12/28

CPC classification number: H04L45/02 ,  H04L45/42 ,  H04L45/48 ,  H04L45/66

Abstract: Methods, apparatus and systems for routing information flows in networks based on spanning trees and network switching element resources. One or more controllers are used to assign information flows to network switching elements (NSEs) through use of spanning trees derived from link path costs. NSEs generate status information relating to resources they employ to facilitate information flows that is sent to the controller(s). The status information is used to derive link costs, which are then used to generate spanning trees that support routing between the NSEs without any path loops. Information flows are assigned to the NSEs such that the routing paths for the flows use the links in the spanning tree. The link costs and spanning trees are dynamically computed during ongoing operations, enabling the network routing and flow assignments to be reconfigured in response to dataplane events and changes to the information flow traffic.

Abstract translation: 基于生成树和网络交换单元资源在网络中路由信息流的方法，装置和系统。 一个或多个控制器用于通过使用从链路路径开销导出的生成树来向网络交换元件（NSE）分配信息流。 NSE产生与他们采用的资源相关的状态信息，以便于发送给控制器的信息流。 状态信息用于导出链路成本，然后用于生成支持NSE之间路由的生成树，而不需要任何路径循环。 信息流被分配给NSE，使得流的路由路径使用生成树中的链路。 在正在进行的操作期间动态地计算链路成本和生成树，使得可以响应于数据平台事件和对信息流量的改变来重新配置网络路由和流分配。

公开(公告)号：US20130301475A1

公开(公告)日：2013-11-14

申请号：US13915706

申请日：2013-06-12

Applicant: Iosif Gasparakis ,  Mark D. Gray

Inventor： Iosif Gasparakis ,  Mark D. Gray

IPC: H04L12/24

CPC classification number: H04L47/2441 ,  H04L41/08 ,  H04L43/026 ,  H04L47/24 ,  H04L47/2408 ,  H04L69/22

Abstract: An embodiment may include circuitry to be included, at least in part, in at least one node in a network. The circuitry may generate, at least in part, and/or receive, at least in part, at least one packet. The packet may be received, at least in part, by at least one switch node in the network. The switch node may designate, in response at least in part to the packet, at least one port of the switch node to be used to facilitate, at least in part, establishment, at least in part, of at least one path for propagation of at least one flow between at least two other nodes in the network. The packet may be generated based at least in part upon (1) at least one application classification, (2) at least one allocation request, and (3) network resource availability information.

Abstract translation: 一个实施例可以包括至少部分地在网络中的至少一个节点中包括的电路。 该电路至少部分地可以至少部分地生成至少一个分组。 该分组可以至少部分地由网络中的至少一个交换节点接收。 交换节点可以至少部分地指定分组响应于交换节点的至少一个端口，以用于至少部分地促进至少一个路径的传播， 在网络中的至少两个其他节点之间的至少一个流。 至少部分地基于（1）至少一个应用分类，（2）至少一个分配请求和（3）网络资源可用性信息来生成分组。

公开(公告)号：US20170289068A1

公开(公告)日：2017-10-05

申请号：US15088910

申请日：2016-04-01

Applicant: Stephen T. Palermo ,  Iosif Gasparakis ,  Scott P. Dubal ,  Kapil Sood ,  Trevor Cooper ,  Jr-Shian Tsai ,  Jesse C. Brandeburg ,  Andrew J. Herdrich ,  Edwin Verplanke

Inventor： Stephen T. Palermo ,  Iosif Gasparakis ,  Scott P. Dubal ,  Kapil Sood ,  Trevor Cooper ,  Jr-Shian Tsai ,  Jesse C. Brandeburg ,  Andrew J. Herdrich ,  Edwin Verplanke

IPC: H04L12/861 ,  H04L12/931 ,  G06F15/173 ,  H04L12/715

CPC classification number: H04L49/9047 ,  G06F9/45558 ,  G06F15/17331 ,  G06F2009/45595 ,  H04L45/64 ,  H04L49/70

Abstract: Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.

公开(公告)号：US20140153568A1

公开(公告)日：2014-06-05

申请号：US13995978

申请日：2012-05-10

Applicant: Iosif Gasparakis

Inventor： Iosif Gasparakis

IPC: H04L12/717

CPC classification number: H04L45/42 ,  H04L5/0058 ,  H04L45/38 ,  H04L49/00 ,  H04L49/505

Abstract: A system for network routing based on resource availability. A network switching element (NSE) may be configured to provide status information to a controller. The controller may be configured to utilize the status information in determining control information that may be provided to the NSE. The NSE may further be configured to assign processing of information flows to processors in the NSE based on the control information. For example, the control information may contain minimum and maximum percent utilization levels for the processors. Information flows may be reassigned to processors that have available processing capacity from processors whose operation is determined not to be in compliance with the minimum and maximum levels. Moreover, inactive processors may be deactivated and alerts may be sent to the controller when the NSE determines that no available processing capacity exists to reassign the flows of processors whose operation is determined to be noncompliant.

Abstract translation: 基于资源可用性的网络路由系统。 网络交换元件（NSE）可以被配置为向控制器提供状态信息。 控制器可以被配置为在确定可以提供给NSE的控制信息中使用状态信息。 NSE还可以被配置为基于控制信息将处理信息流分配给NSE中的处理器。 例如，控制信息可以包含用于处理器的最小和最大利用百分比。 信息流可以被重新分配给具有可处理能力的处理器，处理器的操作被确定为不符合最小和最大级别。 此外，当NSE确定不存在可用的处理能力以重新分配其操作被确定为不符合的处理器的流时，可以停用非活动处理器并且可以向控制器发送警报。

公开(公告)号：US20140059170A1

公开(公告)日：2014-02-27

申请号：US13976460

申请日：2012-05-02

Applicant: Iosif Gasparakis ,  Peter P. Waskiewicz, JR. ,  Ilango S. Ganga ,  Terry V. Hulett ,  Parathasarathy Sarangam

Inventor： Iosif Gasparakis ,  Peter P. Waskiewicz, JR. ,  Ilango S. Ganga ,  Terry V. Hulett ,  Parathasarathy Sarangam

IPC: H04L29/08

CPC classification number: H04L67/02 ,  G06F9/45533 ,  H04L69/321

Abstract: Examples are disclosed for a device having at least two media access controllers. In some examples, a first media access controller may be coupled to a host computing device. A second media access controller may be coupled to one or more processor circuits arranged to perform packet processing of data payloads for one or more data frames forwarded through the first media access controller and/or forwarded through the second media access controller. The first media access controller may be coupled to the second media access controller via a communication link. Other examples are described and claimed.

Abstract translation: 公开了具有至少两个媒体访问控制器的设备的示例。 在一些示例中，第一媒体访问控制器可以耦合到主计算设备。 第二媒体接入控制器可以耦合到一个或多个处理器电路，其被布置为对通过第一媒体接入控制器转发的一个或多个数据帧执行数据有效载荷的分组处理和/或通过第二媒体接入控制器转发。 第一媒体接入控制器可以经由通信链路耦合到第二媒体接入控制器。 其他的例子被描述和要求保护。

公开(公告)号：US20130318303A1

公开(公告)日：2013-11-28

申请号：US13993620

申请日：2012-03-22

Applicant: Iosif Gasparakis ,  Peter P. Waskiewicz, JR.

Inventor： Iosif Gasparakis ,  Peter P. Waskiewicz, JR.

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F9/5016 ,  G06F2209/5014

Abstract: Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.

Abstract translation: 描述了用于直接I / O的缓存的应用保留使用的介质，方法和系统的实施例。 一种使用应用预留高速缓存的方法可以包括：由多个核心中的一个核心执行的应用程序使用多个级别的高速缓存中的一个级别的第一部分， 并且由多个核心中的一个核心将与应用程序相关联的数据从计算设备的输入/输出（I / O）设备直接传送到高速缓存的多个级别之一的第一部分。 可以描述和要求保护其他实施例。