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43 条记录 (耗时 0.035 秒)

    Multiplexer for semiconductor memory device
    16.
    发明授权
    Multiplexer for semiconductor memory device 失效
    用于半导体存储器件的多路复用器

    公开(公告)号：US5825235A

    公开(公告)日：1998-10-20

    申请号：US649763

    申请日：1996-05-15

    申请人： Jong Hoon Oh

    发明人： Jong Hoon Oh

    IPC分类号： G11C8/00 ,  G11C7/10 ,  H03K17/693 ,  H03K17/62

    CPC分类号： H03K17/693 ,  G11C7/1078

    摘要： A multiplexer for a semiconductor memory device which has at least two pads for inputting data signals from the outside. The multiplexer has at least two input lines for inputting the data signals from the at least two pads, respectively, at least two control lines for inputting control signals for switching the data signals from the at least two input lines, respectively, and at least two switching circuits, each of the at least two switching circuits transferring the data signal from a corresponding one of the at least two input lines to an output line in response to the control signal from a corresponding one of the at least two control lines and having a floating node formed to be electrically isolable from the output line and the corresponding input line to prevent a loss of the data signal on the output line. According to the present invention, the multiplexer can prevent a data loss due to a disturbance and accurately transfer the data signals from the at least two pads.

    摘要翻译： 一种用于半导体存储器件的多路复用器，其具有用于从外部输入数据信号的至少两个焊盘。 多路复用器具有至少两条输入线，用于分别输入来自至少两个焊盘的数据信号，至少两条控制线，用于输入用于分别从至少两条输入线切换数据信号的控制信号和至少两条输入线 开关电路，所述至少两个开关电路中的每一个响应于来自所述至少两个控制线中的相应一个控制线的控制信号将所述数据信号从所述至少两个输入线中的相应一个输入线传输到输出线，并且具有 浮动节点形成为与输出线和相应的输入线电隔离，以防止输出线上的数据信号的损失。 根据本发明，多路复用器可以防止由于干扰引起的数据丢失并且精确地传送来自至少两个焊盘的数据信号。

    Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors
    17.
    发明授权
    Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors 有权
    用于在可编程处理器上运行MPEG-2 AAC或MPEG-4AAC音频解码算法的计算电路和方法

    公开(公告)号：US07805477B2

    公开(公告)日：2010-09-28

    申请号：US11342765

    申请日：2006-01-30

    申请人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

    发明人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

    IPC分类号： G06F17/14

    CPC分类号： G10L19/16

    摘要： The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

    摘要翻译： 本发明涉及用于在可编程处理器上用作多声道高质量音频系统中的音频压缩算法的有效运行MPEG-2AAC或MPEG-4AAC算法的计算电路和方法。 根据本发明，可以有效地执行在实施MPEG-2 / 4AAC算法中占用大量部分操作的IMDCT处理。 另外，虽然现有的数字信号处理器的架构仍然被使用，但通过添加地址生成器，霍夫曼解码器和位处理架构的架构，可以提高性能。 毕竟，设计和改变可编程处理器是方便的。

    INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES
    18.
    发明申请
    INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES 有权
    集成电路，包括多个存储器件

    公开(公告)号：US20090031077A1

    公开(公告)日：2009-01-29

    申请号：US11781374

    申请日：2007-07-23

    申请人： Ralf Klein ,  Jong Hoon Oh

    发明人： Ralf Klein ,  Jong Hoon Oh

    IPC分类号： G06F12/00 ,  G06F13/38

    CPC分类号： G06F13/4239

    摘要： An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.

    摘要翻译： 集成电路包括数据总线和耦合到数据总线的第一存储器件。 第一存储器件被配置为响应于完成第一存储器件的加电序列而提供第一信号。 集成电路包括耦合到数据总线的第二存储器件。 第二存储器件被配置为响应于完成第二存储器件的加电序列来提供第二信号。 集成电路包括控制器，被配置为基于第一信号和第二信号来访问第一存储器件和第二存储器件。

    Method and apparatus for early write termination in a semiconductor memory
    19.
    发明授权
    Method and apparatus for early write termination in a semiconductor memory 失效
    半导体存储器中早期写入终止的方法和装置

    公开(公告)号：US07414899B2

    公开(公告)日：2008-08-19

    申请号：US11414570

    申请日：2006-04-28

    申请人： Jong Hoon Oh ,  Alan Deng

    发明人： Jong Hoon Oh ,  Alan Deng

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1027 ,  G11C7/1072 ,  G11C11/4076

    摘要： A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

    摘要翻译： 响应于在写入操作期间检测到对其施加的数据选通信号的去激活，同步DRAM（SDRAM）终止写入操作。 在一个示例中，SDRAM包括缓冲电路和早期写入终止电路。 缓冲电路被配置为响应于在写入操作期间施加到SDRAM的数据选通信号来采样输入数据，并将输入数据引导到用于存储输入数据的SDRAM的一个或多个存储器单元。 早期写入终止电路被配置为响应于检测到数据选通信号的去激活而禁止在存储采样的输入数据之后访问一个或多个存储器单元，以小于编程的突发长度来终止写入操作。