公开(公告)号：US08200730B2

公开(公告)日：2012-06-12

申请号：US12880720

申请日：2010-09-13

申请人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

发明人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

IPC分类号： G06F17/14

CPC分类号： G10L19/16

摘要： The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

摘要翻译： 本发明涉及用于在可编程处理器上用作多声道高质量音频系统中的音频压缩算法的有效运行MPEG-2AAC或MPEG-4AAC算法的计算电路和方法。 根据本发明，可以有效地执行在实施MPEG-2 / 4AAC算法中占用大量部分操作的IMDCT处理。 另外，虽然现有的数字信号处理器的架构仍然被使用，但是通过添加地址生成器，霍夫曼解码器和位处理架构的架构，可以提高性能。 毕竟，设计和改变可编程处理器是方便的。

公开(公告)号：US07805477B2

公开(公告)日：2010-09-28

申请号：US11342765

申请日：2006-01-30

申请人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

发明人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

IPC分类号： G06F17/14

CPC分类号： G10L19/16

摘要： The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

摘要翻译： 本发明涉及用于在可编程处理器上用作多声道高质量音频系统中的音频压缩算法的有效运行MPEG-2AAC或MPEG-4AAC算法的计算电路和方法。 根据本发明，可以有效地执行在实施MPEG-2 / 4AAC算法中占用大量部分操作的IMDCT处理。 另外，虽然现有的数字信号处理器的架构仍然被使用，但通过添加地址生成器，霍夫曼解码器和位处理架构的架构，可以提高性能。 毕竟，设计和改变可编程处理器是方便的。

公开(公告)号：US07333036B2

公开(公告)日：2008-02-19

申请号：US11342764

申请日：2006-01-30

申请人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

发明人： Jong Hoon Oh ,  Myung Hoon Sunwoo ,  Jong Ha Moon

IPC分类号： H03M7/40

CPC分类号： H03M7/40 ,  G10L19/16

摘要： The present invention relates to the computing method and Huffman computing circuits for improving the correctness and efficiency of the nonlinear inverse quantization when the MPEG-2 AAC (Advanced Audio Coding) or MPEG-4 AAC algorithm which is used as an audio compression algorithm in multi-channel high-quality audio systems is implemented on programmable processors. In accordance with the present invention, while the architecture of the existing digital signal processor is reused, the performance can be improved by means of the addition of Huffman decoder and bit processing architecture. Accordingly, to design and change the programmable processor can be facilitated.

摘要翻译： 本发明涉及当用作多声道压缩算法的MPEG-2AAC（高级音频编码）或MPEG-4AAC算法时，用于提高非线性逆量化的正确性和效率的计算方法和霍夫曼计算电路 通道高品质音频系统在可编程处理器上实现。 根据本发明，在现有的数字信号处理器的结构被重用的同时，通过加入霍夫曼解码器和比特处理架构可以提高性能。 因此，可以方便设计和改变可编程处理器。

公开(公告)号：US07944047B2

公开(公告)日：2011-05-17

申请号：US11860985

申请日：2007-09-25

申请人： Jong Hoon Oh ,  Klaus Hummler ,  Oliver Kiehl ,  Josef Schnell ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Lee Ward Collins ,  Octavian Beldiman

发明人： Jong Hoon Oh ,  Klaus Hummler ,  Oliver Kiehl ,  Josef Schnell ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Lee Ward Collins ,  Octavian Beldiman

IPC分类号： H01L21/00 ,  H01L23/34

CPC分类号： H01L25/105 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

摘要： Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

摘要翻译： 本发明的实施例通常提供用于改变多芯片封装（MCP）的功能而不需要完全替换MCP的技术和装置。 MCP可以被设计成具有顶部封装衬底，其被设计为与由MCP接收的附加封装相连接，改变MCP的功能。

公开(公告)号：US07882324B2

公开(公告)日：2011-02-01

申请号：US11928633

申请日：2007-10-30

申请人： Josef Schnell ,  Klaus Hummler ,  Jong Hoon Oh ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Oliver Kiehl ,  Octavian Beldiman ,  Lee Ward Collins

发明人： Josef Schnell ,  Klaus Hummler ,  Jong Hoon Oh ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Oliver Kiehl ,  Octavian Beldiman ,  Lee Ward Collins

IPC分类号： G06F12/00

CPC分类号： G06F13/1689 ,  G06F1/10 ,  G11C7/22 ,  G11C2207/2254

摘要： Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

摘要翻译： 本发明的实施例通常提供用于访问存储器的系统，方法和存储器件。 一个实施例包括被配置为确定第一存储器设备和第二存储器设备之间的定时偏差的同步电路，并且向第一存储器设备和第二存储器设备中的至少一个引入增量延迟以调整定时偏差。

公开(公告)号：US07688665B2

公开(公告)日：2010-03-30

申请号：US11860977

申请日：2007-09-25

申请人： Jung Pill Kim ,  Jong Hoon Oh ,  Oliver Kiehl ,  Josef Schnell ,  Klaus Hummler ,  Wayne Frederick Ellis ,  Octavian Beldiman ,  Lee Ward Collins

发明人： Jung Pill Kim ,  Jong Hoon Oh ,  Oliver Kiehl ,  Josef Schnell ,  Klaus Hummler ,  Wayne Frederick Ellis ,  Octavian Beldiman ,  Lee Ward Collins

IPC分类号： G11C5/14

CPC分类号： H01L23/5286 ,  H01L23/3128 ,  H01L23/50 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

摘要翻译： 本发明的实施例通常提供用于在多芯片封装（MCP）的器件之间共享内部产生的电压的装置和技术。 内部产生的电压可以通过电耦合器件并承载内部产生的电压的导电结构来共享。

公开(公告)号：US20090113078A1

公开(公告)日：2009-04-30

申请号：US11930450

申请日：2007-10-31

申请人： JOSEF SCHNELL ,  Klaus Hummler ,  Jong Hoon Oh ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Oliver Kiehl ,  Octavian Beldiman ,  Lee Ward Collins

发明人： JOSEF SCHNELL ,  Klaus Hummler ,  Jong Hoon Oh ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Oliver Kiehl ,  Octavian Beldiman ,  Lee Ward Collins

IPC分类号： G06F13/28

CPC分类号： G11C7/10 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1078 ,  G11C7/109

摘要： Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

摘要翻译： 本发明的实施例通常提供用于访问存储器的系统，方法和存储器装置。 在一个实施例中，第一存储器设备包括命令解码逻辑，其被配置为解码发出到第一存储器设备的命令和第二存储器设备，同时绕过第二存储器设备的命令解码逻辑。

公开(公告)号：US20070252292A1

公开(公告)日：2007-11-01

申请号：US11699492

申请日：2007-01-30

申请人： Sang Keun Choi ,  Tae Ho Joo ,  Jong Hoon Oh ,  Eun Ha Lee ,  Hyoung Min Go

发明人： Sang Keun Choi ,  Tae Ho Joo ,  Jong Hoon Oh ,  Eun Ha Lee ,  Hyoung Min Go

IPC分类号： B29D11/00 ,  A23G1/22 ,  B29C69/00

CPC分类号： B29C45/14434 ,  B29C45/14065

摘要： A mold unit manufacturing a plastic edged glass shelf includes a first mold including a first support frame forming groove; a second mold including a second support frame forming groove; a support frame forming portion formed by the first and second support frame forming grooves; a seating portion receiving a glass sheet; and support pins formed in the support frame forming portion forming the edge of the glass sheet.

摘要翻译： 制造塑料边玻璃架的模具单元包括：第一模具，包括第一支撑框架形成槽; 第二模具，包括第二支撑框架形成槽; 由所述第一和第二支撑框架形成槽形成的支撑框架形成部分; 容纳玻璃板的座位部; 以及形成在形成玻璃板的边缘的支撑框架形成部分中的支撑销。

公开(公告)号：US20060262843A1

公开(公告)日：2006-11-23

申请号：US11192293

申请日：2005-07-28

申请人： Tae Ho Kim ,  Jong Hoon Oh

发明人： Tae Ho Kim ,  Jong Hoon Oh

IPC分类号： H03K7/08

CPC分类号： H03F3/217 ,  H03F1/26 ,  H03F1/305 ,  H03F2200/342 ,  H03F2200/351

摘要： A pulse width modulator for use in a digital amplifier, includes a pop noise reducer for reducing pop noise by controlling a width and a phase of a pulse of a PWM signal output from the pulse width modulator, wherein the pop noise reducer contains: a PWM pulse register for storing a width and a phase values of a pulse of the PWM signal; and a pulse generator for outputting the PWM signal according to the values stored in the PWM pulse register. The pulse width modulator reduces pop noise generated when power supply to a digital amplifier is started and interrupted.

公开(公告)号：US5825235A

公开(公告)日：1998-10-20

申请号：US649763

申请日：1996-05-15

申请人： Jong Hoon Oh

发明人： Jong Hoon Oh

IPC分类号： G11C8/00 ,  G11C7/10 ,  H03K17/693 ,  H03K17/62

CPC分类号： H03K17/693 ,  G11C7/1078

摘要： A multiplexer for a semiconductor memory device which has at least two pads for inputting data signals from the outside. The multiplexer has at least two input lines for inputting the data signals from the at least two pads, respectively, at least two control lines for inputting control signals for switching the data signals from the at least two input lines, respectively, and at least two switching circuits, each of the at least two switching circuits transferring the data signal from a corresponding one of the at least two input lines to an output line in response to the control signal from a corresponding one of the at least two control lines and having a floating node formed to be electrically isolable from the output line and the corresponding input line to prevent a loss of the data signal on the output line. According to the present invention, the multiplexer can prevent a data loss due to a disturbance and accurately transfer the data signals from the at least two pads.

摘要翻译： 一种用于半导体存储器件的多路复用器，其具有用于从外部输入数据信号的至少两个焊盘。 多路复用器具有至少两条输入线，用于分别输入来自至少两个焊盘的数据信号，至少两条控制线，用于输入用于分别从至少两条输入线切换数据信号的控制信号和至少两条输入线 开关电路，所述至少两个开关电路中的每一个响应于来自所述至少两个控制线中的相应一个控制线的控制信号将所述数据信号从所述至少两个输入线中的相应一个输入线传输到输出线，并且具有 浮动节点形成为与输出线和相应的输入线电隔离，以防止输出线上的数据信号的损失。 根据本发明，多路复用器可以防止由于干扰引起的数据丢失并且精确地传送来自至少两个焊盘的数据信号。