公开(公告)号：US07668015B2

公开(公告)日：2010-02-23

申请号：US12005366

申请日：2007-12-27

Applicant: Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

Inventor： Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC: G11C16/04

CPC classification number: G11C11/5628

Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

Abstract translation: 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

公开(公告)号：US09261940B2

公开(公告)日：2016-02-16

申请号：US13396618

申请日：2012-02-15

Applicant: Bo-geun Kim ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

Inventor： Bo-geun Kim ,  Kye-hyun Kyung ,  Jae-yong Jeong ,  Seung-hun Choi ,  Seok-cheon Kwon ,  Chul-ho Lee

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F1/32 ,  G06F1/14 ,  G06F13/16 ,  G06F1/04 ,  G11C7/22

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

Abstract: A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract translation: 存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与该处理器时钟同步地执行峰值电流产生操作的存储器 内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

公开(公告)号：USRE45577E1

公开(公告)日：2015-06-23

申请号：US13151735

申请日：2011-06-02

Applicant: Bum-soo Kim ,  Gui-Yong Lee ,  Jong-Min Kim ,  Ji-hyun In ,  Je-sung Kim ,  Sam-hyuk Noh ,  Sang-lyul Min ,  Dong-hee Lee ,  Jae-yong Jeong ,  Yoo-kun Cho ,  Jong-moo Choi

Inventor： Bum-soo Kim ,  Gui-Yong Lee ,  Jong-Min Kim ,  Ji-hyun In ,  Je-sung Kim ,  Sam-hyuk Noh ,  Sang-lyul Min ,  Dong-hee Lee ,  Jae-yong Jeong ,  Yoo-kun Cho ,  Jong-moo Choi

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/42 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/7203

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.

Abstract translation: 提供闪存管理方法。 根据该方法，当向预先写入数据的页面写入预定数据的请求时，将预定数据写入对应于包含页面的数据块的日志块。 当接收到将预定数据再次写入页面的请求时，将预定数据写入日志块中的空闲空闲页面。 即使请求连续写入同一页面，管理方法也可以在一个日志块中进行处理，从而提高闪存资源的使用效率。

公开(公告)号：US08214618B2

公开(公告)日：2012-07-03

申请号：US12216380

申请日：2008-07-02

Applicant: Jae-yong Jeong

Inventor： Jae-yong Jeong

IPC: G06F12/00

CPC classification number: G06F12/10 ,  G06F11/203 ,  G06F12/0223

Abstract: A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.

Abstract translation: 一种基于多核系统中的访问时间的存储器管理方法和装置。 在多核系统的存储器管理方法中，可以容易地估计由处理核心执行的任务的执行时间，并且当通过处理核心之间迁移任务时可以确保相同的存储器访问时间 根据与处理核心对应的从处理核心到存储器的距离设置存储器分配顺序，将要由处理核心之一处理的逻辑地址根据所设置的存储器分配顺序转换为处理核心之一的物理地址 存储器，并将与所翻译的物理地址相对应的存储器分配给处理核心。

公开(公告)号：US20090193287A1

公开(公告)日：2009-07-30

申请号：US12216380

申请日：2008-07-02

Applicant: Jae-yong Jeong

Inventor： Jae-yong Jeong

IPC: G06F12/02 ,  G06F11/20

CPC classification number: G06F12/10 ,  G06F11/203 ,  G06F12/0223

Abstract: A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same memory access time when a task is migrated between processing cores by setting a memory allocation order according to distances from the processing cores to the memories in correspondence with the processing cores, translating a logical address to be processed by one of the processing cores according to the set memory allocation order into a physical address of one of the memories, and allocating a memory corresponding to the translated physical address to the processing core.

Abstract translation: 一种基于多核系统中的访问时间的存储器管理方法和装置。 在多核系统的存储器管理方法中，可以容易地估计由处理核心执行的任务的执行时间，并且当通过处理核心之间迁移任务时可以确保相同的存储器访问时间 根据与处理核心对应的从处理核心到存储器的距离设置存储器分配顺序，将要由处理核心之一处理的逻辑地址根据所设置的存储器分配顺序转换为处理核心之一的物理地址 存储器，并将与所翻译的物理地址相对应的存储器分配给处理核心。

公开(公告)号：US20080170443A1

公开(公告)日：2008-07-17

申请号：US12003589

申请日：2007-12-28

Applicant: Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

Inventor： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC: G11C16/06

CPC classification number: G11C16/3454

Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

Abstract translation: 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。