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21 条记录 (耗时 0.028 秒)

    Address transition detector circuit
    12.
    发明授权
    Address transition detector circuit 失效
    地址转换检测电路

    公开(公告)号：US5198709A

    公开(公告)日：1993-03-30

    申请号：US721050

    申请日：1991-06-26

    申请人： Cormac M. O'Connell

    发明人： Cormac M. O'Connell

    IPC分类号： G11C11/41 ,  H03K5/1534 ,  H03K19/21

    CPC分类号： H03K5/1534 ,  H03K19/215

    摘要： A semiconductor integrated circuit including a detection circuit (e.g. an address transition detector) for detecting a change of a first and a second input signal. The detection circuit includes a first and a second resettable delay circuit and a gate circuit which is connected thereto. The gate circuit receives directly both the input signals and the output signals of the delay circuits for promptly outputting an output pulse signal with a minimum duration T for all durations of input signals.

    Encryption processor with shared memory interconnect
    14.
    发明授权
    Encryption processor with shared memory interconnect 有权
    具有共享内存互连的加密处理器

    公开(公告)号：US06434699B1

    公开(公告)日：2002-08-13

    申请号：US09584930

    申请日：2000-06-01

    申请人： David E. Jones ,  Cormac M. O'Connell

    发明人： David E. Jones ,  Cormac M. O'Connell

    IPC分类号： G06F124

    CPC分类号： G06F7/5324 ,  G06F7/49931 ,  G06F7/5052 ,  G06F7/72 ,  G06F7/722 ,  G06F2207/382 ,  G06F2207/3828 ,  H04L9/14 ,  H04L2209/125

    摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

    摘要翻译： 加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。 该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。 通过双端口存储器在处理元件之间传送数据。 中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。 通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。 乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

    Random access memory with page addressing mode
    16.
    发明授权
    Random access memory with page addressing mode 失效
    具有页寻址模式的随机存取存储器

    公开(公告)号：US5245585A

    公开(公告)日：1993-09-14

    申请号：US604729

    申请日：1990-10-22

    申请人： Peter H. Voss ,  Cormac M. O'Connell

    发明人： Peter H. Voss ,  Cormac M. O'Connell

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C7/1021 ,  G11C7/1033

    摘要： In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

    Encryption processor with shared memory interconnect
    18.
    再颁专利
    Encryption processor with shared memory interconnect 有权
    具有共享内存互连的加密处理器

    公开(公告)号：USRE44697E1

    公开(公告)日：2014-01-07

    申请号：US13603137

    申请日：2012-09-04

    申请人： David E. Jones ,  Cormac M. O'Connell

    发明人： David E. Jones ,  Cormac M. O'Connell

    IPC分类号： G06F21/00

    CPC分类号： G06F7/5324 ,  G06F7/49931 ,  G06F7/5052 ,  G06F7/72 ,  G06F7/722 ,  G06F2207/382 ,  G06F2207/3828 ,  H04L9/14 ,  H04L2209/125

    摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

    摘要翻译： 加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。 该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。 通过双端口存储器在处理元件之间传送数据。 中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。 通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。 乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

    Television tuner
    19.
    发明授权
    Television tuner 失效

    公开(公告)号：US06995808B2

    公开(公告)日：2006-02-07

    申请号：US10053603

    申请日：2002-01-24

    申请人： Stephen J. Kovacic ,  Cormac M. O'Connell

    发明人： Stephen J. Kovacic ,  Cormac M. O'Connell

    IPC分类号： H04N5/50 ,  H04N5/455

    CPC分类号： H04N21/4263 ,  H03J1/0008 ,  H04N5/50

    摘要： A front end tuner for receiving TV signals and the like includes a frequency conversion circuit including a mixer for beating a local signal with received signals within a predetermined band of frequencies to provide selected signals within a predetermined band of frequencies to provide selected signals within a predetermined channel band of frequencies. A signal converter circuit generates digitally encoded signal representations of the selected signals. The frequency conversion circuit and the signal converter circuit are in a form of an integrated circuit within a semiconductor substrate. In a TV receiver, on-following digital processing of the digitally encoded signals is performed in a microcomputer. In one example a channel selection code is used by the microcomputer to synthesize the local oscillator signal and in another example the signal converter circuit is a codec, responsive to codes from the microprocessor, to supply a control voltage for controlling a local oscillator. From time to time channel selection is automatically fine tuned.