公开(公告)号：US5087840A

公开(公告)日：1992-02-11

申请号：US657334

申请日：1991-02-13

申请人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, decease ,  by Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Leonardus C. M. G. Pfennings, decease ,  by Henricus J. Kunnen, legal representative ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： G11C11/413 ,  G11C7/10 ,  H03K19/0948

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106

摘要： An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

公开(公告)号：US5040152A

公开(公告)日：1991-08-13

申请号：US265640

申请日：1988-11-01

申请人： Peter H. Voss ,  Leonardus C. M. G. Pfennings ,  Cormac M. O'Connell ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Peter H. Voss ,  Leonardus C. M. G. Pfennings ,  Cormac M. O'Connell ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C8/12 ,  G11C11/401 ,  G11C11/408 ,  H01L27/10

CPC分类号： G11C5/025 ,  G11C8/12

摘要： A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.

摘要翻译： 静态RAM存储器针对速度进行了优化。 存储器分为主存储矩阵，每个主存储矩阵分为存储块。 存储器块被分组，每组具有共同的地址位，然而每个组耦合到单独的焊盘或焊盘组。 这些焊盘在封装上互连到公共封装引脚。

公开(公告)号：US4929911A

公开(公告)日：1990-05-29

申请号：US296462

申请日：1989-05-22

申请人： Thomas J. Davies ,  Evert Seevinck ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kennen ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

发明人： Thomas J. Davies ,  Evert Seevinck ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kennen ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Hans Ontrop

IPC分类号： H03K19/0185 ,  H03K17/687 ,  H03K19/003

CPC分类号： H03K19/00315

摘要： A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

公开(公告)号：US5033024A

公开(公告)日：1991-07-16

申请号：US453637

申请日：1989-12-20

申请人： Cormac M. O'Connell ,  Leonardus Pfennings, deceased ,  by Henricus J. Kunnen, executor ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

发明人： Cormac M. O'Connell ,  Leonardus Pfennings, deceased ,  by Henricus J. Kunnen, executor ,  Peter H. Voss ,  Thomas J. Davies ,  Hans Ontrop ,  Cathal G. Phelan

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/846

摘要： An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

公开(公告)号：US5212413A

公开(公告)日：1993-05-18

申请号：US726470

申请日：1991-07-08

申请人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

发明人： Cathal G. Phelan ,  Peter H. Voss ,  Thomas J. Davies ,  Cormac M. O'Connell ,  Leonardus C. M. G. Pfennings, deceased ,  Henricus J. Kunnen, legal representative ,  Hans Ontrop

IPC分类号： H03K19/173 ,  G11C29/04 ,  H03K3/356

CPC分类号： H03K3/356008

摘要： When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

公开(公告)号：US4931667A

公开(公告)日：1990-06-05

申请号：US266172

申请日：1988-11-02

申请人： Leonardus C. M. G. Pfennings ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Thomas J. Davies ,  Hans Ontrop

发明人： Leonardus C. M. G. Pfennings ,  Peter H. Voss ,  Cormac M. O'Connell ,  Cathal G. Phelan ,  Thomas J. Davies ,  Hans Ontrop

IPC分类号： G06F3/00 ,  G11C7/10 ,  G11C11/409 ,  G11C11/41 ,  G11C11/419

CPC分类号： G11C7/1048

摘要： Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

摘要翻译： 通过由差分放大器评估的差分信号经由双总线传输数据，特别是出于防止干扰的原因。 然而，这种差分放大器仅具有有限的输入电压范围，或其中不能操作的输入信号的死电压范围。 为了防止两条总线上的电压进入该死区，由于总线上的共模干扰信号或由于差分放大器的馈电电压的电压下降，两条总线被连接 根据本发明，调整电路使得两个总线的电压在死电压范围之外的方向上改变相同的量。 这可以防止差分放大器的未指定条件，而不会明显影响两条总线上的差分信号。 描述了集成存储器的应用。

公开(公告)号：US5157284A

公开(公告)日：1992-10-20

申请号：US724099

申请日：1991-07-01

申请人： Cormac M. O'Connell ,  Peter H. Voss

发明人： Cormac M. O'Connell ,  Peter H. Voss

IPC分类号： G11C11/417 ,  G11C8/06 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C8/06

摘要： Using a NAND and a NOR gate as input gates provides a simple and efficient input buffer. In the input buffer circuit, a chip select signal is applied in inverted form to the NOR gate and in non-invented form to the NAND gate. The resulting input buffer is both simpler and faster than earlier circuits.

公开(公告)号：US5245585A

公开(公告)日：1993-09-14

申请号：US604729

申请日：1990-10-22

申请人： Peter H. Voss ,  Cormac M. O'Connell

发明人： Peter H. Voss ,  Cormac M. O'Connell

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C7/1021 ,  G11C7/1033

摘要： In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

公开(公告)号：USRE37944E1

公开(公告)日：2002-12-31

申请号：US09434331

申请日：1999-11-05

申请人： Dennis A. Fielder ,  James H. Derbyshire ,  Peter B. Gillingham ,  Randy R. Torrance ,  Cormac M. O'Connell

发明人： Dennis A. Fielder ,  James H. Derbyshire ,  Peter B. Gillingham ,  Randy R. Torrance ,  Cormac M. O'Connell

IPC分类号： G06F1576

CPC分类号： G09G5/363 ,  G09G5/39 ,  G11C7/10 ,  G11C7/1048 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104

摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

摘要翻译： 一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中 作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。

公开(公告)号：USRE44589E1

公开(公告)日：2013-11-12

申请号：US12819467

申请日：2010-06-21

申请人： James H. Derbyshire ,  Peter B. Gillingham ,  Randy R. Torrance ,  Cormac M. O'Connell

发明人： Dennis A. Fielder ,  James H. Derbyshire ,  Peter B. Gillingham ,  Randy R. Torrance ,  Cormac M. O'Connell

IPC分类号： G06F13/14 ,  G06F15/00 ,  G06F12/02 ,  G09G5/36

CPC分类号： G09G5/363 ,  G09G5/39 ,  G11C7/10 ,  G11C7/1048 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104

摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.