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1.发明授权Integrated logic circuit having a control circuit for generating a time-dependent waveform 失效具有用于产生时间相关波形的控制电路的集成逻辑电路
公开(公告)号：US4783601A
公开(公告)日：1988-11-08
申请号：US9428
申请日：1987-02-02
IPC分类号： H03K17/687 , H03K5/02 , H03K17/16 , H03K19/003 , H03K19/0185 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/56 , H03K3/01 , H03K5/13
CPC分类号： H03K19/00361 , H03K17/163 , H03K5/023
摘要： An integrated logic circuit includes an output circuit for generating an output current which increases linearly in time. In integrated logic circuits the problem presents itself that the rapid variation of the (dis) charging of a data output causes a reverse voltage pulse VL across the inductance formed by the connection wires. The reverse voltage is limited by causing the charge or discharge current (for the load capacities present) to increase linearly to a maximum permissible value. This is done by driving the output field effect transistor with a control voltage VC which varies in time in the form of a square root.
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公开(公告)号：US4616339A
公开(公告)日：1986-10-07
申请号：US618006
申请日：1984-06-06
CPC分类号： G11C16/12
摘要： Field effect transistors having a short channel length are desirable for carrying out logic operations at a high speed. However, they are then not capable of withstanding the comparatively high programming and erasing voltage at which an (E)EPROM has to be operated. During the programming cycle the field effect transistors are kept in the current-nonconducting state, while recording the logic information obtained by the logic operations, the "fast" transistors are nevertheless capable of withstanding the comparatively high voltage.
摘要翻译： 具有短信道长度的场效应晶体管对于高速执行逻辑运算是理想的。 然而，它们不能承受必须操作（E）EPROM的相对较高的编程和擦除电压。 在编程周期期间，场效应晶体管保持在电流 - 非导通状态，同时记录通过逻辑运算获得的逻辑信息，但是“快速”晶体管仍能承受较高的电压。
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公开(公告)号：US4920287A
公开(公告)日：1990-04-24
申请号：US265660
申请日：1988-11-01
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/78 , H03K17/10 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/00315
摘要： A digital circuit with a 5 V power supply voltage in which NMOS transistors constructed in sub-micron technology are protected against excessive field strengths by means of additional transistors in order to prevent so-called "hot carrier stress" for this purpose the additional transistors have a greater channel length and/or a higher threshold voltage.
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4.发明授权Semiconductor memory circuit having a fast read amplifier tristate bus driver 失效具有快速读取放大器三态总线驱动器的半导体存储电路
公开(公告)号：US4910714A
公开(公告)日：1990-03-20
申请号：US315184
申请日：1989-02-24
IPC分类号： G11C11/419 , G11C7/06
CPC分类号： G11C7/062
摘要： A C-MOS semiconductor memory circuit includes a read amplifier and a tristate bus driver. The read amplifier is a two stage amplifier. The bit lines in the memory are connected via P-MOS pull-up transistors to the supply voltage. The logic low level is 1 Volt below the supply voltage. In order to bring the input signals for the difference amplifier at a most sensitive and fast level, a d.c.-shifting amplifier of the "emitter follower" type is connected between each input thereof and the associated bit line. The difference amplifier and the two follower amplifiers are activated only for a short period of time by means of a selection signal which gives a strong restriction in the power dissipation. The tristate driver comprises a push-pull output stage and an inverting AND gate which is controlled by the output of a difference amplifier and by an equalization signal which is also applied to the difference amplifier and therefore is of a simple design and gives only a low signal delay.
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公开(公告)号：US5086331A
公开(公告)日：1992-02-04
申请号：US643687
申请日：1991-01-18
IPC分类号： G11C17/06 , G06K19/073 , G11C11/22 , G11C14/00 , G11C17/04 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115
CPC分类号： G11C17/04 , G11C11/22 , H01L27/115
摘要： The invention relates to an integrated circuit having a programmable cell, more particularly for use in an electronic card. The cell is provided with a programmable element (P) having two conductive layers (51, 52), which are separated from each other by a dielectric layer (53). The element can be programmed by applying between the layers 51, 52 a programming voltage such that an electric breakdown is produced in the dielectric layer (53), as a result of which the element passes permanently from an electrically non-conducting state to an electrically conducting state. According to the invention, the programmable cell comprises an asymmetric bistable trigger circuit (I,II). The trigger circuit (I,II) is loaded with the element (P) in such a manner that during operation it is in a first state if the element is electrically non-conducting and is in a second state if the element is electrically conducting.
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公开(公告)号：US4644250A
公开(公告)日：1987-02-17
申请号：US692153
申请日：1985-01-17
CPC分类号： G11C16/12
摘要： In order to prevent an excessively fast rise of the programming voltage for an (E)EPROM, a stage is inserted which on the one hand prevents voltage losses and which on the other hand realizes the required large time constant of the voltage rise in spite of the use of small capacitances.
摘要翻译： 为了防止（E）EPROM的编程电压的过快上升，插入一级，一方面防止电压损失，另一方面实现电压上升所需的大时间常数，尽管 使用小电容。
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7.发明授权Static RAM having a precharge operation which exhibits reduced hot electron stress 失效具有表现出减少的热电子应力的预充电操作的静态RAM
公开(公告)号：US5038326A
公开(公告)日：1991-08-06
申请号：US617306
申请日：1990-11-19
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： G11C11/4125 , G11C11/412 , G11C11/419
摘要： A memory cell is read by first charging a pair of bit lines to given positive potentials and then raising the potential of a cell access line to render access transistors conductive. The cell supply voltage is sufficient to cause substantial hot-electron stress in the n-channel transistors of the cell if it were applied directly across their source-drain paths while they were conductive. However, a limit is imposed on the maximum positive potentials which are applied to the bit lines from the exterior, and on the minimum ratio of the sizes of the cell n-channel amplifier transistors to the sizes of the access transistors, taking into account the threshold voltages of the amplifier transistors, and as a result substantial hot-electron stress does not occur. Substantial hot-electron stress is also prevented during a write operation by arranging that this is effectively preceded by a read operation.
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8.发明授权
公开(公告)号：US4723229A
公开(公告)日：1988-02-02
申请号：US825842
申请日：1986-02-04
IPC分类号： G11C11/44 , G11C8/00 , G11C8/12 , G11C11/418 , G11C11/40
CPC分类号： G11C8/12 , G11C11/418
摘要： The invention relates to a (static) memory which is divided into a number of memory blocks, memory cells being arranged in rows and columns in each memory block. A row in a memory block is activated via a selection gate whereto there are applied an inverted row selection signal (which is applied to all memory blocks) and a non-inverted and an inverted block selection signal (which is applied to all section gates in a memory block). The selection gate comprises a P-MOS transistor and two parallel-connected N-MOS transistors. The junction between the P-MOS and the N-MOS transistors constitutes the gate output (for activating a row of cells). The row selection signal is applied to the gate electrode of the PMOS transistor and of a first N-MOS transistor. The inverted block selection signal is applied to the gate electrode of the other N-MOS transistor and the block selection signal is applied to the main electrode of the P-MOS transistor.
摘要翻译： 本发明涉及一种（静态）存储器，其被分成多个存储器块，每个存储块中以行和列排列存储单元。 通过选择门激活存储器块中的一行，其中施加了反相行选择信号（其被应用于所有存储器块）和非反相和反相块选择信号（其被应用于 一个记忆块）。 选择栅极包括P-MOS晶体管和两个并联的N-MOS晶体管。 P-MOS和N-MOS晶体管之间的结点构成栅极输出（用于激活一行单元）。 行选择信号被施加到PMOS晶体管的栅电极和第一N-MOS晶体管。 反向块选择信号被施加到另一个N-MOS晶体管的栅电极，并且块选择信号被施加到P-MOS晶体管的主电极。
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公开(公告)号：US4707807A
公开(公告)日：1987-11-17
申请号：US806313
申请日：1985-12-09
CPC分类号： G11C14/00
摘要： A memory and a non-volatile, programmable, static memory cell in which a programmable transistor and a capacitance are added to a known static memory cell. The cross-wise couplings between the transistors of the static cell form a first and a second junction. The gate and a main electrode (drain) of the programmable transistor are connected to the first junction. The second junction is connected to an injection location opposite the floating gate of the programmable transistor whose channel is connected in series with the capacitance the other side of which is connected to the sources of the two transistors of the static cell.
摘要翻译： 存储器和非易失性，可编程的静态存储单元，其中可编程晶体管和电容被添加到已知的静态存储单元。 静电单元的晶体管之间的交叉耦合形成第一和第二结。 可编程晶体管的栅极和主电极（漏极）连接到第一结。 第二结连接到与可编程晶体管的浮动栅极相对的注入位置，该可编程晶体管的沟道与其另一侧的静电电容的两个晶体管的源极连接的电容串联连接。
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公开(公告)号：US4603402A
公开(公告)日：1986-07-29
申请号：US677639
申请日：1984-12-04
IPC分类号： G11C17/00 , G11C16/04 , G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/10 , G11C16/14 , H01L29/7881 , H01L29/7883
摘要： The invention relates to an EPROM or an EEPROM in which the information is stored in the form of electrical charge above the channel region of a MOST, as a result of which the threshold voltage of the MOST is determined by the stored information. Writing/erasing of the memory generally requires high voltages to cause charge current to flow through an insulating layer to and from the charge storage region. In order to avoid having the parasitic MOSTs becoming conductive, means are provided by which during operation a small reverse bias is applied to the sources of these parasitic transistors, as a result of which due to the high k factor the threshold voltage of the parasitic transistors increases considerably. This does not require additional logic because use can be made of the generator in the reading circuit, which generates a suitable small voltage.
摘要翻译： 本发明涉及一种EPROM或EEPROM，其中信息以MOST的信道区域上方的电荷形式存储，结果MOST的阈值电压由存储的信息确定。 存储器的写入/擦除通常需要高电压以使充电电流通过电荷存储区域中的绝缘层流过绝缘层。 为了避免使寄生MOST变得导通，提供了在操作期间向这些寄生晶体管的源极施加小的反向偏压的装置，其结果是由于高k因子，寄生晶体管的阈值电压 大大增加 这不需要额外的逻辑，因为可以在读取电路中使用发生器，从而产生合适的小电压。
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