公开(公告)号：US08097500B2

公开(公告)日：2012-01-17

申请号：US12013846

申请日：2008-01-14

Applicant: Takashi Ando ,  Eduard A. Cartier ,  Changhwan Choi ,  Elizabeth A. Duch ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  James Pan ,  Vamsi K. Paruchuri

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Changhwan Choi ,  Elizabeth A. Duch ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  James Pan ,  Vamsi K. Paruchuri

IPC: H01L21/00

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.

Abstract translation: 在一个实施例中，本发明是用于制造高性能带边互补金属氧化物半导体器件的方法和装置。 用于制造互补金属氧化物半导体器件的方法的一个实施例包括使用栅极第一工艺制造n型金属氧化物半导体器件，以及使用栅极最后工艺制造p型金属氧化物半导体器件 。

公开(公告)号：US20110263086A1

公开(公告)日：2011-10-27

申请号：US13179460

申请日：2011-07-08

Applicant: James Pan

Inventor： James Pan

IPC: H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L29/161 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a field effect transistor (FET) includes forming a carbon-containing region over a substrate. An epitaxial layer is formed over the carbon-containing region. The epitaxial layer has a lower doping concentration than the substrate. A body region of a first conductivity type is formed in the epitaxial layer. The epitaxial layer is of a second conductivity type and forms a p-n junction with the body region. Gate electrodes are formed adjacent to but insulated from the body regions. Source regions of the second conductivity type are formed in the body regions. The source regions form p-n junctions with the body regions.

Abstract translation: 形成场效应晶体管（FET）的方法包括在衬底上形成含碳区域。 在含碳区域上形成外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层中形成第一导电类型的体区。 该外延层具有第二导电类型，并与本体区域形成p-n结。 栅电极形成为与身体区域相邻但绝缘。 在身体区域中形成第二导电类型的源极区域。 源极区域与身体区域形成p-n结。

公开(公告)号：US20110244641A1

公开(公告)日：2011-10-06

申请号：US13083253

申请日：2011-04-08

Applicant: James Pan ,  James J. Murphy

Inventor： James Pan ,  James J. Murphy

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66727 ,  H01L29/66734

Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.

Abstract translation: 一种用于形成屏蔽栅极沟道场效应晶体管（FET）的方法包括在半导体区域中形成沟槽，在每个沟槽的底部形成屏蔽电极，并形成在屏蔽电极上延伸的电极间电介质（IED）。 IED可以包括低k电介质。 该方法还包括在IED上的每个沟槽的上部形成栅电极。

公开(公告)号：US20110215377A1

公开(公告)日：2011-09-08

申请号：US13103728

申请日：2011-05-09

Applicant: James Pan ,  Qi Wang

Inventor： James Pan ,  Qi Wang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.

Abstract translation: 垂直导电的平面栅极场效应晶体管包括第一导电类型的硅区域，在硅区域上延伸的硅 - 锗层，横向延伸但与硅 - 锗层绝缘的栅电极，主体区域 在硅 - 锗层和硅区域中延伸的第二导电类型以及在硅 - 锗层中延伸的第一导电类型的源极区域。 栅极电极横向重叠源极和主体区域，使得在源极区域和主体区域的外边界之间直接在栅电极下方延伸的硅锗层的一部分形成沟道区域。

公开(公告)号：US07936009B2

公开(公告)日：2011-05-03

申请号：US12170328

申请日：2008-07-09

Applicant: James Pan ,  James J. Murphy

Inventor： James Pan ,  James J. Murphy

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66727 ,  H01L29/66734

Abstract: A shielded gate trench field effect transistor (FET) comprises trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench. The shield electrode is insulated from the semiconductor region by a shield dielectric. A gate electrode is disposed in each trench over the shield electrode, and an inter-electrode dielectric (IED) comprising a low-k dielectric extends between the shield electrode and the gate electrode.

Abstract translation: 屏蔽栅沟槽场效应晶体管（FET）包括延伸到半导体区域的沟槽。 屏蔽电极设置在每个沟槽的底部。 屏蔽电极通过屏蔽电介质与半导体区域绝缘​​。 栅极电极设置在屏蔽电极上的每个沟槽中，并且包括低k电介质的电极间电介质（IED）在屏蔽电极和栅电极之间延伸。

公开(公告)号：US07825465B2

公开(公告)日：2010-11-02

申请号：US12330273

申请日：2008-12-08

Applicant: James Pan ,  Qi Wang

Inventor： James Pan ,  Qi Wang

IPC: H01L29/78

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

Abstract translation: 沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。 第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。 每个主体区域与硅区域形成第一PN结，并且每个主体区域包括在相邻沟槽之间横向延伸的第二导电类型的硅 - 锗层。 第一导电体的源区在沟槽的侧面，并且每个源极区域与身体区域之一形成第二PN结。 通道区域沿着源区域和身体区域的底表面之间的沟槽的侧壁在身体区域中延伸。 硅 - 锗层延伸到相应的沟道区，从而降低沟道电阻。

公开(公告)号：US07772668B2

公开(公告)日：2010-08-10

申请号：US11964283

申请日：2007-12-26

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/93

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7831

Abstract: A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

Abstract translation: 场效应晶体管（FET）包括延伸到半导体区域中的一对沟槽。 每个沟槽包括在沟槽的下部中的第一屏蔽电极和在沟槽的上部中的与屏蔽电极绝缘的栅电极。 第一导电类型的第一和第二阱区域在该对沟槽之间的半导体区域中横向延伸并邻接该对沟槽的侧壁。 第一和第二阱区域通过第二导电类型的第一漂移区域彼此垂直间隔开。 栅电极和第一屏蔽电极相对于第一阱区和第二阱区定位，使得当FET被置于导通状态时，在第一和第二阱区中的每一个中形成沟道。

公开(公告)号：US20100013009A1

公开(公告)日：2010-01-21

申请号：US12333707

申请日：2008-12-12

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66727 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66734 ,  H01L29/7397

Abstract: A field effect transistor includes body regions of a first conductivity type over a semiconductor region of a second conductivity type such that the body regions form p-n junctions with the semiconductor region. Trenches extend through the body region and terminate within the semiconductor region. Source regions of the second conductivity type extend over the body regions adjacent the trenches such that the source regions form p-n junctions with the body regions. A gate dielectric layer lines sidewalls of each trench. A metal liner lines the gate dielectric layer in each trench. A gate electrode comprising metallic material is disposed in each trench.

Abstract translation: 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的主体区域，使得主体区域与半导体区域形成p-n结。 沟槽延伸穿过身体区域并终止在半导体区域内。 第二导电类型的源极区域在与沟槽相邻的主体区域上延伸，使得源极区域与主体区域形成p-n结。 栅极电介质层对每个沟槽的侧壁进行排列。 金属衬垫在每个沟槽中排列栅极电介质层。 包括金属材料的栅电极设置在每个沟槽中。

公开(公告)号：US07622348B2

公开(公告)日：2009-11-24

申请号：US11616858

申请日：2006-12-28

Applicant: James Pan

Inventor： James Pan

IPC: H01L21/8242

CPC classification number: H01L21/76897 ,  H01L21/28568 ,  H01L21/288 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

Abstract: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

Abstract translation: 提供了用于在制造包括逻辑和存储器的IC中减小与位线的触点的纵横比的方法。 该方法包括以下步骤：形成将由金属的第一级接触的第一组器件区域和与第二级金属接触的第二组存储器位线，该第一级与第二级与第二级分开 至少一层介电材料。 导电材料通过化学镀在器件区域和位线上进行电镀，并且第一和第二导电插塞形成在导电材料上。 第一导电插头与第一级金属接触，第二导电插头与第二级金属接触。 镀覆的导电材料的厚度提供了一种自对准的方法，用于减小导电插头的纵横比。

公开(公告)号：US20090194811A1

公开(公告)日：2009-08-06

申请号：US12330273

申请日：2008-12-08

Applicant: James Pan ,  Qi Wang

Inventor： James Pan ,  Qi Wang

IPC: H01L29/78

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a first PN junction with the silicon region, and each body region includes a silicon-germanium layer of the second conductivity type laterally extending between adjacent trenches. Source regions of the first conductivity flank the trenches, and each source region forms a second PN junction with one of the body regions. Channel regions extend in the body regions along sidewalls of the trenches between the source regions and a bottom surface of the body regions. The silicon-germanium layers extend into corresponding channel regions to thereby reduce the channel resistance.

Abstract translation: 沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。 第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。 每个体区与硅区形成第一PN结，并且每个体区包括在相邻沟槽之间横向延伸的第二导电类型的硅 - 锗层。 第一导电体的源区在沟槽的侧面，并且每个源极区域与身体区域之一形成第二PN结。 通道区域沿着源区域和身体区域的底表面之间的沟槽的侧壁在身体区域中延伸。 硅 - 锗层延伸到相应的沟道区，从而降低沟道电阻。