公开(公告)号：US09660039B2

公开(公告)日：2017-05-23

申请号：US15062887

申请日：2016-03-07

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Arichika Ishida ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 μm and less than or equal to 30 μm. The source line and the drain line extend in directions different from each other.

公开(公告)号：US09613860B2

公开(公告)日：2017-04-04

申请号：US14996323

申请日：2016-01-15

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L29/49 ,  H01L21/78

CPC classification number: H01L21/76895 ,  H01L21/022 ,  H01L21/32136 ,  H01L21/465 ,  H01L21/78 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.

公开(公告)号：US20210141256A1

公开(公告)日：2021-05-13

申请号：US17126112

申请日：2020-12-18

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

公开(公告)号：US09947798B2

公开(公告)日：2018-04-17

申请号：US14804395

申请日：2015-07-21

Applicant: Japan Display Inc.

Inventor： Hidekazu Miyake ,  Arichika Ishida ,  Norihiro Uemura ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: G02F1/136 ,  H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  G02F1/1368

CPC classification number: H01L29/7869 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to one embodiment, a display device includes thin-film transistor. The thin-film transistor includes a first semiconductor layer, a first insulating film, a gate electrode, a second insulating film, a second semiconductor layer, a first electrode and a second electrode. The gap between the bottom surface of the gate electrode and the upper surface of the first channel region of the first semiconductor layer is larger than the gap between the upper surface of the gate electrode and the bottom surface of the second channel region of the second semiconductor layer.

公开(公告)号：US09618813B2

公开(公告)日：2017-04-11

申请号：US14990201

申请日：2016-01-07

Applicant: Japan Display Inc.

Inventor： Yohei Yamaguchi ,  Arichika Ishida ,  Hidekazu Miyake ,  Hiroto Miyake ,  Isao Suzumura

IPC: G02F1/1362 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1368

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/13685 ,  G02F2202/10 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78633 ,  H01L29/7869

Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.

公开(公告)号：US20160268417A1

公开(公告)日：2016-09-15

申请号：US15062887

申请日：2016-03-07

Applicant: Japan Display Inc.

Inventor： Hidekazu MIYAKE ,  Arichika Ishida ,  Hiroto Miyake ,  Isao Suzumura ,  Yohei Yamaguchi

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/78696

Abstract: According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 μm and less than or equal to 30 μm. The source line and the drain line extend in directions different from each other.

Abstract translation: 根据一个实施例，薄膜晶体管包括半导体层SC，其包括沟道区，沟道区两侧的源极区和漏极区，栅极GE，连接到源极区的第一电极SE 经由第一接触孔CH1，经由第二接触孔CH2连接到漏极区的第二电极DE，连接到第一电极的源极线和连接到第二电极的漏极线。 从沟道宽度方向到第一和第二接触孔到各个区域的端部的距离大于或等于5μm且小于或等于30μm。 源极线和漏极线在彼此不同的方向上延伸。

公开(公告)号：US20160012782A1

公开(公告)日：2016-01-14

申请号：US14793106

申请日：2015-07-07

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Arichika Ishida ,  Norihiro Uemura ,  Hidekazu Miyake ,  Hiroto Miyake ,  Yohei Yamaguchi

IPC: G09G3/36

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/136227 ,  H01L27/1288

Abstract: According to one embodiment, a display device includes a TFT on an insulating substrate. The TFT includes a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and a source electrode and a drain electrode each provided in contact with at least a part of the semiconductor layer. The source and drain electrodes have a laminated structure including a lower layer, an intermediate layer and an upper layer. The source and drain electrodes include sidewalls each including a first tapered portion on the upper layer side, a second tapered portion on the lower layer side and a sidewall protective film attached to the second tapered portion. The taper angle of the first tapered portion is smaller than that of the second tapered portion.

Abstract translation: 根据一个实施例，显示装置包括在绝缘基板上的TFT。 TFT包括栅极电极，栅电极上的绝缘层，绝缘层上的半导体层，以及各自设置成与半导体层的至少一部分接触的源电极和漏电极。 源电极和漏电极具有包括下层，中间层和上层的层压结构。 源电极和漏电极包括侧壁，其各自包括上层侧的第一锥形部分，下层侧上的第二锥形部分和附接到第二锥形部分的侧壁保护膜。 第一锥形部的锥角小于第二锥形部的锥角。