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    Chip package structure
    11.
    发明申请
    Chip package structure 失效
    芯片封装结构

    公开(公告)号：US20050098872A1

    公开(公告)日：2005-05-12

    申请号：US10974728

    申请日：2004-10-28

    Applicant: Jeffrey Lien

    Inventor： Jeffrey Lien

    IPC: H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48

    CPC classification number: H01L23/4951 ,  H01L23/3114 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: This invention relates to a chip package structure comprising of a chip, multiple leads with inner and outer ends, an exposed chip upper surface, an encapsulated body encloses the peripherals of the chip, and multiple conducting wires used to connect electrically the chip and leads, wherein said leads extends inward to the surfaces on the two sides of the chip, in the mean time, pasting method is used to connect the two side surfaces of the chip to the leads in order to carry the chip, therefore, traditional die pad is replaced, furthermore, the outer ends or surfaces of the leads are exposed out of encapsulated body, this is to prevent solder overflow and enhance solder aggregation effect, in the mean time, packaging cost can be saved and easier visual positioning and rework can be obtained from this package structure, leads are used as terminals to be electrically connected to the external; therefore, through the inward extended leads structure, die pad is replaced, and the effects of package volume reduction, heat dissipation enhancement, packaging material cost saving and excellent, stable electrical connection are reached through this package structure.

    Abstract translation: 本发明涉及一种芯片封装结构，其包括芯片，具有内端和外端的多根引线，暴露的芯片上表面，封装芯片周边的封装体以及用于将芯片和引线电连接的多根导线， 其中所述引线向内延伸到芯片两侧的表面，同时，使用粘贴方法将芯片的两个侧表面连接到引线以便承载芯片，因此传统的芯片焊盘是 此外，引线的外端或表面被封装体露出，这是为了防止焊料溢出并增强焊料聚集效应，同时可以节省包装成本，并且可以获得更容易的视觉定位和返工 从该封装结构，引线用作端子以电连接到外部; 因此，通过向内延伸的引线结构，更换了管芯焊盘，通过封装结构达到了封装体积减小，散热增强，封装材料节省成本以及优异，稳定的电气连接的效果。

    Chip package structure
    12.
    发明授权
    Chip package structure 失效
    芯片封装结构

    公开(公告)号：US07309918B2

    公开(公告)日：2007-12-18

    申请号：US10974728

    申请日：2004-10-28

    Applicant: Jeffrey Lien

    Inventor： Jeffrey Lien

    IPC: H01L23/34

    CPC classification number: H01L23/4951 ,  H01L23/3114 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: This invention relates to a chip package structure comprising of a chip, multiple leads with inner and outer ends, an exposed chip upper surface, an encapsulated body encloses the peripherals of the chip, and multiple conducting wires used to connect electrically the chip and leads, wherein said leads extends internally to the surfaces on the two sides of the chip, in the mean time, pasting method is used to connect the two side surfaces of the chip to the leads in order to carry the chip, therefore, traditional die pad is replaced, furthermore, the outer ends or lower surfaces of the leads are exposed out of encapsulated body, this is to prevent solder overflow and enhance solder aggregation effect, in the mean time, packaging cost can be saved and easier visual positioning and rework can be obtained from this package structure, leads are used as terminals to be electrically connected to the external; therefore, through the internally extended leads structure, die pad is replaced, and the effects of package volume reduction, heat dissipation enhancement, packaging material cost saving and good, stable electrical connection are reached through this package structure.

    Abstract translation: 本发明涉及一种芯片封装结构，其包括芯片，具有内端和外端的多根引线，暴露的芯片上表面，封装芯片周边的封装体以及用于将芯片和引线电连接的多根导线， 其中所述引线内部延伸到芯片两侧的表面，同时，使用粘贴方法将芯片的两个侧表面连接到引线以便承载芯片，因此传统的芯片焊盘是 此外，引线的外端或下表面从封装体露出，这是为了防止焊料溢出和增强焊料聚集效应，同时可以节省包装成本，更容易的视觉定位和返工 从该封装结构获得的引线用作与外部电连接的端子; 因此，通过内部延伸的引线结构，替代了芯片焊盘，通过封装结构达到封装体积减小，散热增强，封装材料成本节省和良好的稳定电连接的效果。

    Manufacturing method of a modularized leadframe
    13.
    发明授权
    Manufacturing method of a modularized leadframe 失效
    模块化引线框架的制造方法

    公开(公告)号：US07204017B2

    公开(公告)日：2007-04-17

    申请号：US10959205

    申请日：2004-10-07

    Applicant: Jeffrey Lien ,  Shihlin Chang

    Inventor： Jeffrey Lien ,  Shihlin Chang

    IPC: H01R43/00

    CPC classification number: H01L23/3114 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73265 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A manufacturing method of a modularized leadframe, using a first mold set to contact and hold the upper surface of rows of multiple block leads, using a second mold set to contact and hold at least one selected surface of the lower surface of leads, the second mold set has a protruding part between each row of leads so that the upper surface of the protruding part be in close contact with the inner surface of the first mold set. The hollow space between the mold sets is then injected with packaging materials such that a leadframe structure having packaged and fixed leads therein and surfaces for wire-bonding and soldering is obtained. A packaging material filling space is formed in the leadframe after removing the first and the second mold sets.

    Abstract translation: 一种模块化引线框架的制造方法，使用第一模具组来接触并保持多个块引线的行的上表面，使用第二模具组来接触和保持引线的下表面的至少一个选定表面，第二模具组 模具组在每排引线之间具有突出部分，使得突出部分的上表面与第一模具组的内表面紧密接触。 然后，使用包装材料注入模具组之间的中空空间，从而获得其中具有封装和固定引线的引线框结构以及用于引线接合和焊接的表面。 在去除第一和第二模具组之后，在引线框架中形成包装材料填充空间。

    Concealable chip leadframe unit structure
    16.
    发明申请
    Concealable chip leadframe unit structure 失效
    可控芯片引线框单元结构

    公开(公告)号：US20050156290A1

    公开(公告)日：2005-07-21

    申请号：US10959207

    申请日：2004-10-07

    Applicant: Jeffrey Lien ,  Yuan Cheng

    Inventor： Jeffrey Lien ,  Yuan Cheng

    IPC: H01L21/58 ,  H01L23/31 ,  H01L23/495

    CPC classification number: H01L23/49551 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A concealable chip leadframe unit structure is disclosed which is made up of multiple lead units arranged in order, each lead in the lead unit is formed by pressing and comprising of a piece body with upper placement plane, the lower surface of the piece body is pressed to form at least an inner conducting plane which can be connected to the chip, and at least one protruding bump is formed adjacent to the inner conducting plane, the end surface of the protruding bump is used as an out-conducting plane to be connected to outside; in this structure, chip can be attached to the upper placement plane of the lead structure, and the inner conducting plane can be connected to the chip through metallic wire.

    Abstract translation: 公开了一种可隐藏的芯片引线框单元结构，其由依次布置的多个引线单元构成，引线单元中的每个引线通过压制形成，并且包括具有上放置平面的片体，片体的下表面被按压 至少形成能够连接到芯片的内部导电平面，并且与内部导电平面相邻地形成至少一个突出凸块，突出凸起的端面用作与外部导电平面连接的导电平面 外; 在该结构中，芯片可以安装在引线结构的上部放置平面上，并且内部导电平面可以通过金属线连接到芯片。

    Circuit board having deposit holes
    18.
    发明申请
    Circuit board having deposit holes 审中-公开
    电路板有沉积孔

    公开(公告)号：US20050121224A1

    公开(公告)日：2005-06-09

    申请号：US10959214

    申请日：2004-10-07

    Applicant: Jeffrey Lien

    Inventor： Jeffrey Lien

    IPC: H05K1/18 ,  H05K1/02

    CPC classification number: H05K1/183 ,  H05K1/182 ,  H05K2201/09036 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10651 ,  H05K2201/10689

    Abstract: The present invention relates to the structural design of a circuit board having deposit holes. The design is to allocate one or more deposit holes that are either caved in or penetrate through the board at locations specified by the spatial layout, as well as to set step-like holes on a multilayer circuit board. On the panel surrounding the edge of the deposit holes, circuit contacts are provided for connecting electronic components (for example IC transistors, connectors, resistors, capacitors, or other circuit boards), such that when placed in deposit holes, they can be welded or fixed via the circuit contacts.

    Abstract translation: 本发明涉及具有沉积孔的电路板的结构设计。 该设计是分配一个或多个沉积孔，这些沉积孔在由空间布局指定的位置处被插入或穿过板，以及在多层电路板上设置阶梯状孔。 在围绕沉积孔边缘的面板上，提供电路触点用于连接电子部件（例如，IC晶体管，连接器，电阻器，电容器或其他电路板），使得当放置在沉积孔中时，它们可以被焊接或 通过电路触点固定。

    Assembly structure for hiding electronic components
    19.
    发明申请
    Assembly structure for hiding electronic components 审中-公开
    用于隐藏电子元件的装配结构

    公开(公告)号：US20050117314A1

    公开(公告)日：2005-06-02

    申请号：US10959167

    申请日：2004-10-07

    Applicant: Jeffrey Lien

    Inventor： Jeffrey Lien

    IPC: H05K1/16 ,  H05K1/18 ,  H05K7/06

    CPC classification number: H05K1/182 ,  H05K1/183 ,  H05K2201/09036 ,  H05K2201/09845 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10689

    Abstract: The present invention is related to an assembly structure for hiding electronic components, that is, at least one containing hole penetrating through a PCB being set on a predetermined location of the PCB, circuits being arranged on at least one surface of a predetermined side edge of the containing hole, the containing hole being capable of reserving at least one electronic component (IC chip, resistance, capacitance or LED, etc.) so as to that at least one leg of the electronic component extending and connecting to the circuits of the surface for welding, the assembly structure for hiding electronic components is therefore formed.

    Abstract translation: 本发明涉及一种用于隐藏电子部件的组装结构，即至少一个穿过PCB的容纳孔设置在PCB的预定位置上，电路布置在预定侧面的至少一个表面上 容纳孔，容纳孔能够保留至少一个电子部件（IC芯片，电阻，电容或LED等），使得电子部件的至少一个支腿延伸并连接到表面的电路 为了焊接，因此形成用于隐藏电子部件的组装结构。

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