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11.发明授权Integrating/SAR ADC and method with low integrator swing and low complexity 有权集成/ SAR ADC和低积分摆幅和低复杂度的方法公开(公告)号：US07511648B2
公开(公告)日：2009-03-31
申请号：US12072968
申请日：2008-02-29
IPC分类号： H03M3/00
摘要： A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.
摘要翻译： 可重构电路（10）包括积分器（30），其具有用于选择性地将输入电容器（C0,1,2,3,6,7）和积分电容器（C4,5）耦合到积分器的端子的开关（SW1-6） （30），用于操作混合Δ-Σ/ SAR ADC（400），以便产生等于第一电压（DeltaVbe）和第二电压（Vbe）之和的参考电压值（Vref）。 执行第一次积分以减小积分器输出电压摆幅。 如果比较器（22）耦合到积分器，则如果比较器不改变状态，则将第二电压（Vbe）积分在第一方向上。如果比较器（22）耦合到积分器，则将积分器的残余（Vresidue）乘以2.然后， 。 第一电压（DeltaVbe）集成在使积分器输出电压（Vout）等于2xVresidue-Vref或2xVresidue + Vref的方向上。
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12.发明授权Digital to analog converter architecture and method having low switch count and small output impedance 有权具有低开关数和小输出阻抗的数模转换器结构和方法公开(公告)号：US07501970B2
公开(公告)日：2009-03-10
申请号：US11880568
申请日：2007-07-23
IPC分类号： H03M1/66
摘要： A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to produce coarse resolution node voltages (V0, . . . V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,1 . . . ) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout1), the second output voltage (Vout1) and the first output voltage (Vout2) providing a differential analog output signal (Vout1−Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.
摘要翻译： 数模转换器包括耦合在第一电压（Vin）和中间电压（V0）之间以产生粗分辨率节点电压（V0，...，V240）的粗分辨率电阻器电路（11），并且还包括精细分辨率 电阻电路（20）耦合在中间电压和第二电压（GND）之间。 响应于数字输入（D0,1 ...）的一组MSB位来选择粗分辨率节点电压之一以产生第一输出电压（Vout2），并且选择精细分辨率节点电压中的一个 响应于数字输入的一组LSB位以产生第二输出电压（Vout1），第二输出电压（Vout1）和提供差分模拟输出信号（Vout1-Vout2）的第一输出电压（Vout2）。 在一个实施例中，粗分辨率和精细分辨率电阻电路是串电阻电路，在另一实施例中，它们是修改的R-2R网络。
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公开(公告)号：US07495589B1
公开(公告)日：2009-02-24
申请号：US11901355
申请日：2007-09-17
IPC分类号： H03M1/06
摘要： Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).
摘要翻译： 通过将经增益调整的LSB大小基于测量的增益误差存储在存储器（44）中，在包括积分器（17），比较器（30）和数字滤波器（37）的ADC芯片中校正增益误差。 经增益调整的LSB大小被施加到数字滤波器，以使得根据比较器（30）的第一或第二状态，增加经调整的LSB大小值被添加到数字滤波器的累积内容或从累积内容中减去， 在ADC的每个周期。 ADC所需的所有周期之后的最终累加内容是增益校正的数字输出信号（Dout（增益校正））。
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公开(公告)号：US20090009239A1
公开(公告)日：2009-01-08
申请号：US11890204
申请日：2007-08-03
IPC分类号： H03F1/02
CPC分类号： H03F3/45968 , H03F3/387 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03F2203/45212
摘要： An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin−) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).
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15.发明申请Systems and Methods for Temperature Measurement Using N-Factor Coefficient Correction 有权使用N因子系数校正进行温度测量的系统和方法公开(公告)号：US20080259989A1
公开(公告)日：2008-10-23
申请号：US11738595
申请日：2007-04-23
CPC分类号： G01K7/01 , G01K15/00 , G01K2219/00
摘要： Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems. Such temperature measurement systems include a variable current source and a diode connected transistor. The variable current source is capable of applying two or more distinct currents to the diode connected transistor. The currents result in a different base-emitter voltage on the diode connected transistor. The systems further include an n-factor coefficient register and an analog to digital converter. The analog to digital converter is operable to receive two of the base-emitter voltages created by applying the different currents, and to provide a digital output based at least in part on a value stored in the n-factor coefficient register and the two base-emitter voltages.
摘要翻译： 公开了用于温度测量的各种系统和方法。 例如，本发明的一些实施例提供温度测量系统。 这种温度测量系统包括可变电流源和二极管连接的晶体管。 可变电流源能够向二极管连接的晶体管施加两个或更多个不同的电流。 电流导致二极管连接晶体管上的基极 - 发射极电压不同。 该系统还包括一个n因子系数寄存器和一个模数转换器。 模数转换器可操作以接收通过施加不同电流产生的两个基极 - 发射极电压，并且至少部分地基于存储在n因子系数寄存器中的值和两个基极 - 发射极电压。
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16.发明授权Systems and methods for temperature measurement using n-factor coefficient correction 有权使用n因子系数校正的温度测量系统和方法公开(公告)号：US07648271B2
公开(公告)日：2010-01-19
申请号：US11738595
申请日：2007-04-23
CPC分类号： G01K7/01 , G01K15/00 , G01K2219/00
摘要： Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems. Such temperature measurement systems include a variable current source and a diode connected transistor. The variable current source is capable of applying two or more distinct currents to the diode connected transistor. The currents result in a different base-emitter voltage on the diode connected transistor. The systems further include an n-factor coefficient register and an analog to digital converter. The analog to digital converter is operable to receive two of the base-emitter voltages created by applying the different currents, and to provide a digital output based at least in part on a value stored in the n-factor coefficient register and the two base-emitter voltages.
摘要翻译： 公开了用于温度测量的各种系统和方法。 例如，本发明的一些实施例提供温度测量系统。 这种温度测量系统包括可变电流源和二极管连接的晶体管。 可变电流源能够向二极管连接的晶体管施加两个或更多个不同的电流。 电流导致二极管连接晶体管上的基极 - 发射极电压不同。 该系统还包括一个n因子系数寄存器和一个模数转换器。 模数转换器可操作以接收通过施加不同电流产生的两个基极 - 发射极电压，并且至少部分地基于存储在n因子系数寄存器中的值和两个基极 - 发射极电压。
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17.发明申请公开(公告)号：US20080259997A1
公开(公告)日：2008-10-23
申请号：US11738571
申请日：2007-04-23
CPC分类号： G01K7/01 , H03M1/1245
摘要： Various systems and methods for pulse width modulated clocking in a temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems with a variable current source, a transistor, and a pulse width modulation circuit. The variable current source is operable to provide a first current and a second current that are applied to the transistor. A first base-emitter voltage occurs on the transistor when the first current is applied, and a second base-emitter voltage occurs on the transistor when the second current is applied. The first base emitter voltage is associated with a first sample period, and a second base-emitter voltage is associated with a second sample period. The pulse width modulation circuit provides a pulse width modulated clock including a combination of the aforementioned first period and second period.
摘要翻译： 公开了用于温度测量中的脉宽调制时钟的各种系统和方法。 例如，本发明的一些实施例提供具有可变电流源，晶体管和脉宽调制电路的温度测量系统。 可变电流源可操作以提供施加到晶体管的第一电流和第二电流。 当施加第一电流时，在晶体管上发生第一基极 - 发射极电压，并且当施加第二电流时，晶体管上出现第二基极 - 发射极电压。 第一基极发射极电压与第一采样周期相关联，并且第二基极 - 发射极电压与第二采样周期相关联。 脉冲宽度调制电路提供包括上述第一周期和第二周期的组合的脉宽调制时钟。
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18.发明授权公开(公告)号：US07637658B2
公开(公告)日：2009-12-29
申请号：US11738571
申请日：2007-04-23
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , H03M1/1245
摘要： Various systems and methods for pulse width modulated clocking in a temperature measurement are disclosed. For example, some embodiments of the present invention provide temperature measurement systems with a variable current source, a transistor, and a pulse width modulation circuit. The variable current source is operable to provide a first current and a second current that are applied to the transistor. A first base-emitter voltage occurs on the transistor when the first current is applied, and a second base-emitter voltage occurs on the transistor when the second current is applied. The first base emitter voltage is associated with a first sample period, and a second base-emitter voltage is associated with a second sample period. The pulse width modulation circuit provides a pulse width modulated clock including a combination of the aforementioned first period and second period.
摘要翻译： 公开了用于温度测量中的脉宽调制时钟的各种系统和方法。 例如，本发明的一些实施例提供具有可变电流源，晶体管和脉宽调制电路的温度测量系统。 可变电流源可操作以提供施加到晶体管的第一电流和第二电流。 当施加第一电流时，在晶体管上发生第一基极 - 发射极电压，并且当施加第二电流时，晶体管上出现第二基极 - 发射极电压。 第一基极发射极电压与第一采样周期相关联，并且第二基极 - 发射极电压与第二采样周期相关联。 脉冲宽度调制电路提供包括上述第一周期和第二周期的组合的脉宽调制时钟。
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19.发明授权Systems and methods for resistance compensation in a temperature measurement circuit 有权温度测量电路中电阻补偿的系统和方法公开(公告)号：US07524109B2
公开(公告)日：2009-04-28
申请号：US11738584
申请日：2007-04-23
IPC分类号： G01K7/00
摘要： Various systems and methods for temperature measurement are disclosed. For example, some embodiments of the present invention provide methods for temperature measurement that include exciting a provided transistor with at least four sequential input signals of different magnitudes. In response, the transistor exhibits a sequence of output signals corresponding to the four sequential input signals. The sequence of output signals is sensed using a different gain for each of the output signals included in the sequence of output signals, and the output signals included in the sequence of output signals are combined such that the combined output signals eliminates a resistance error. The combined output signals are then used to calculate a temperature of the transistor.
摘要翻译： 公开了用于温度测量的各种系统和方法。 例如，本发明的一些实施例提供了用于温度测量的方法，其包括用至少四个具有不同幅度的顺序输入信号激励所提供的晶体管。 作为响应，晶体管表现出对应于四个顺序输入信号的输出信号序列。 输出信号的序列使用包括在输出信号序列中的每个输出信号的不同的增益来检测，并且包括在输出信号序列中的输出信号被组合，使得组合的输出信号消除了电阻误差。 然后，组合的输出信号用于计算晶体管的温度。
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公开(公告)号：US07380185B2
公开(公告)日：2008-05-27
申请号：US11311833
申请日：2005-12-19
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/3172
摘要： The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit, and for providing a scan data output signal; and wherein the scan data input signal and the scan data output signal share an input/output pin.
摘要翻译： 具有减少的引脚数扫描链的同步逻辑器件包括：多于两个触发器，耦合以形成用于接收扫描数据输入信号的移位寄存器; 用于接收设备输入的组合逻辑电路，为多于两个的触发器产生触发器/触发器输入，并产生输出信号; 第一复用器，用于在测试模式期间向多于两个触发器提供时钟信号; 第二多路复用器，用于在从移位寄存器输出的测试模式和来自组合逻辑电路的输出信号之间进行选择，并用于提供扫描数据输出信号; 并且其中所述扫描数据输入信号和所述扫描数据输出信号共享输入/输出引脚。
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