公开(公告)号：US20110312457A1

公开(公告)日：2011-12-22

申请号：US12819917

申请日：2010-06-21

申请人： Yimin Wang

发明人： Yimin Wang

IPC分类号： F16H55/30

CPC分类号： F16H55/30 ,  F16H55/06

摘要： The present sprocket wheel invention enhances the efficiency of the sprockets made of two materials, e.g., a lighter material at central portion of the sprocket and a hard material at peripheral portion of the sprocket comprising teeth, by drilling half holes on the outer edge of the central portion and half holes on the inner edge of the peripheral portion of the sprocket. In the preferred embodiment, half of the thickness of the sprocket is the entire hole on the peripheral portion of the sprocket with harder materials, and the other half of the thickness of the sprocket is designed to have said half holes for rivets to attach the central portion and the peripheral portion of the sprocket.

摘要翻译： 本链轮轮发明提高了由两种材料制成的链轮的效率，例如，在链轮的中心部分处的较轻的材料和在包括齿的链轮的周边部分处的硬质材料，通过在所述链轮的外边缘上钻出半孔 在链轮的周边部分的内边缘上的中心部分和半孔。 在优选实施例中，链轮的厚度的一半是具有较硬材料的链轮的周边部分上的整个孔，并且链轮的另一半厚度被设计成具有用于铆钉的所述半孔以将中心 部分和链轮的周边部分。

公开(公告)号：US06284594B1

公开(公告)日：2001-09-04

申请号：US09580607

申请日：2000-05-30

申请人： Yong Ju ,  Kai Shao ,  Yimin Wang ,  Shao-Fu Sanford Chu

发明人： Yong Ju ,  Kai Shao ,  Yimin Wang ,  Shao-Fu Sanford Chu

IPC分类号： H01L218242

CPC分类号： H01L27/0629 ,  H01L21/3144 ,  H01L28/40

摘要： A process for simultaneously forming a polysilicon gate structure, for a transfer gate transistor, and a polysilicon top plate, for a capacitor structure, on an underlying planar surface, has been developed. The process features the formation of a polysilicon bottom plate, for the capacitor structure, embedded in a first opening in composite insulator layer, and the formation of an active device region, for a transfer gate transistor structure, via the selective growth of an epitaxial silicon layer, in a second opening of the composite insulator layer, resulting in a planar top surface topography. The presence of this topography reduces the risk of residual polysilicon, present after patterning of the polysilicon gate structure, and of the capacitor, polysilicon top plate.

摘要翻译： 已经开发了用于在底层平面上形成用于电容器结构的传输栅极晶体管和多晶硅顶板的多晶硅栅极结构的工艺。 该方法的特征在于形成多晶硅底板，用于电容器结构，嵌入在复合绝缘体层中的第一开口中，并且通过外延硅的选择性生长形成用于传输栅晶体管结构的有源器件区 层，在复合绝缘体层的第二开口中，产生平坦的顶表面形貌。 这种形貌的存在降低了在多晶硅栅极结构图案化之后存在的残余多晶硅以及电容器，多晶硅顶板的风险。

公开(公告)号：US20150030088A1

公开(公告)日：2015-01-29

申请号：US14089701

申请日：2013-11-25

申请人： Vincent M. K. Chan ,  Yimin Wang

发明人： Vincent M. K. Chan ,  Yimin Wang

IPC分类号： H04N19/86 ,  H04N19/70

CPC分类号： H04N19/42 ,  H04N19/40

摘要： A media processing device includes a transmission interface to transmit an output media stream based on an output clock signal, whereby output video stream includes a representation (e.g., a transcoded representation) of an input media stream. The media processing device further includes a clock drift module to generate a stream of average clock drift values representing differences between a local system time clock and clock references of the input media stream and a proportional-integral-derivative (PID) controller to filter the stream of average clock drift values to generate a stream of filtered average clock drift values. The media processing device further includes a clock adjust module to adjust the output clock signal based on the stream of filtered average clock drift values.

摘要翻译： 媒体处理设备包括：传输接口，用于基于输出时钟信号传输输出媒体流，由此输出视频流包括输入媒体流的表示（例如，转码表示）。 媒体处理设备还包括时钟漂移模块，用于生成表示本地系统时钟与输入媒体流的时钟参考与比例积分微分（PID）控制器之间的差异的平均时钟漂移值流，以过滤流 的平均时钟漂移值，以生成滤波的平均时钟漂移值流。 媒体处理设备还包括时钟调整模块，用于基于滤波的平均时钟漂移值流来调整输出时钟信号。

公开(公告)号：US08921917B2

公开(公告)日：2014-12-30

申请号：US14038410

申请日：2013-09-26

申请人： Yimin Wang

发明人： Yimin Wang

IPC分类号： H01L29/788 ,  H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/088 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

摘要： A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.

摘要翻译： 提供了具有浮动栅极晶体管的分离栅极闪存单元器件。 每个浮栅晶体管通过提供浮置晶体管子结构形成，该浮动栅极晶体管子结构包括设置在设置在公共源的一部分上的栅极氧化物上的多晶硅栅极上的氧化物。 氮化物间隔物沿着浮栅晶体管子结构的侧壁和终止在侧壁处的栅极氧化物的覆盖部分形成。 用氮化物间隔物完整地进行各向同性氧化物蚀刻。 各向同性蚀刻横向后退氧化物的相对边缘，使得氧化物的宽度小于多晶硅栅极的宽度。 在浮栅晶体管子结构之上形成栅极间电介质，并且在栅极间电介质上形成控制栅极以形成浮栅晶体管。

公开(公告)号：US08629514B2

公开(公告)日：2014-01-14

申请号：US13008252

申请日：2011-01-18

申请人： Yimin Wang

发明人： Yimin Wang

IPC分类号： H01L21/02

CPC分类号： H01L21/76229

摘要： A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.

摘要翻译： 一种方法和结构提供了定制STI，浅沟槽隔离，片上系统，SOC或其他半导体集成电路器件的各个部分中的结构。 在单个芯片内，STI结构形成为包括对形成STI结构的SOC芯片的特定器件部分特别有利的不同介电厚度。

公开(公告)号：US08389356B2

公开(公告)日：2013-03-05

申请号：US13045449

申请日：2011-03-10

申请人： Yimin Wang

发明人： Yimin Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/28132 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

摘要翻译： 形成分裂栅极闪存单元结构的方法提供了在形成控制栅极时免于光致抗蚀剂图案的未对准的对称单元。 在闪存单元中使用的浮栅晶体管中使用间隔物来形成浮置栅极。 间隔物可以是用于掩蔽将形成浮动栅极的多晶硅层的氧化物间隔物，或者间隔物可以是本身将形成浮栅的多晶硅间隔物。 浮栅晶体管的栅极间氧化物可以使用HTO形成或者可以沉积。 硬掩模间隔件与控制栅光致抗蚀剂图案化操作结合使用以控制控制栅极的尺寸和配置以及沟道长度。

公开(公告)号：US20120231594A1

公开(公告)日：2012-09-13

申请号：US13045449

申请日：2011-03-10

申请人： Yimin Wang

发明人： Yimin Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/28132 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.

摘要翻译： 形成分裂栅极闪存单元结构的方法提供了在形成控制栅极时免于光致抗蚀剂图案的未对准的对称单元。 在闪存单元中使用的浮栅晶体管中使用间隔物来形成浮置栅极。 间隔物可以是用于掩蔽将形成浮动栅极的多晶硅层的氧化物间隔物，或者间隔物可以是本身将形成浮栅的多晶硅间隔物。 浮栅晶体管的栅极间氧化物可以使用HTO形成或者可以沉积。 硬掩模间隔件与控制栅光致抗蚀剂图案化操作结合使用以控制控制栅极的尺寸和配置以及沟道长度。

公开(公告)号：US20120225528A1

公开(公告)日：2012-09-06

申请号：US13038180

申请日：2011-03-01

申请人： Yimin Wang ,  Raymond Li

发明人： Yimin Wang ,  Raymond Li

IPC分类号： H01L21/336 ,  H01L21/283 ,  H01L21/31

CPC分类号： H01L21/283 ,  H01L21/28273 ,  H01L21/32139 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.

摘要翻译： 用于形成分裂栅极闪存单元存储器件的方法提供了建立浮动栅极区域，然后使用覆盖栅极区域中的栅电极材料的相对边缘的间隔物或其它硬掩模材料，以在蚀刻操作期间用作硬掩模， 部分蚀刻可能是多晶硅的栅电极材料。 如此制造的栅电极用作浮栅电极，并且包括凹入的中心部分，其侧面是一对相对的向上延伸的翅片，其可以在顶点处向上终止。 然后通过热氧化和/或氧化物沉积技术形成浮栅氧化物。

公开(公告)号：US20120223236A1

公开(公告)日：2012-09-06

申请号：US13289936

申请日：2011-11-04

申请人： Kanai S. Shah ,  Charles Brecher ,  Yimin Wang ,  Gary Baldoni ,  William Rhodes

发明人： Kanai S. Shah ,  Charles Brecher ,  Yimin Wang ,  Gary Baldoni ,  William Rhodes

IPC分类号： G01T1/164 ,  C09K11/80 ,  C01F17/00 ,  G01T1/20

CPC分类号： G01T1/202 ,  C01F17/0025 ,  C01P2002/72 ,  C01P2004/01 ,  C01P2004/03 ,  C04B35/44 ,  C04B35/6455 ,  C04B2235/3224 ,  C04B2235/3229 ,  C04B2235/3286 ,  C04B2235/6585 ,  C04B2235/764 ,  C04B2235/768 ,  C04B2235/786 ,  C04B2235/79 ,  C04B2235/81 ,  C04B2235/95 ,  C09K11/7774 ,  G21K4/00

摘要： Scintillator materials based on mixed garnet compositions, as well as corresponding methods and systems, are described.

摘要翻译： 描述了基于混合石榴石组合物的闪烁体材料，以及相应的方法和系统。

公开(公告)号：US20120181592A1

公开(公告)日：2012-07-19

申请号：US13008252

申请日：2011-01-18

申请人： Yimin Wang

发明人： Yimin Wang

IPC分类号： H01L29/788 ,  H01L21/76 ,  H01L29/06

CPC分类号： H01L21/76229

摘要： A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.

摘要翻译： 一种方法和结构提供了定制STI，浅沟槽隔离，片上系统，SOC或其他半导体集成电路器件的各个部分中的结构。 在单个芯片内，STI结构形成为包括对形成STI结构的SOC芯片的特定器件部分特别有利的不同介电厚度。