公开(公告)号：US20050026337A1

公开(公告)日：2005-02-03

申请号：US10628912

申请日：2003-07-28

申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L29/66393 ,  H01L27/11

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P—N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其上形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US20050101102A1

公开(公告)日：2005-05-12

申请号：US10703289

申请日：2003-11-06

申请人： Tze Ho Chan ,  Weining Li ,  Elgin Quek ,  Jia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

发明人： Tze Ho Chan ,  Weining Li ,  Elgin Quek ,  Jia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76237 ,  H01L27/115 ,  H01L29/66825

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。 植入的源极区域形成在有源区域的一侧的沟槽中的一个中。 在有源区的另一侧的另一个沟槽中形成注入的漏极区。 然后在沟槽中形成浅沟槽隔离。 在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。

公开(公告)号：US20050085056A1

公开(公告)日：2005-04-21

申请号：US10689923

申请日：2003-10-17

申请人： Tommy Lai ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Weining Li

发明人： Tommy Lai ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Weining Li

IPC分类号： H01L21/3115 ,  H01L21/314 ,  H01L21/8239 ,  H01L21/8247 ,  H01L21/425 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31155 ,  H01L21/3144 ,  H01L27/1052 ,  H01L27/11546

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

公开(公告)号：US20050148118A1

公开(公告)日：2005-07-07

申请号：US10752357

申请日：2004-01-05

申请人： Jia Zheng ,  Weining Li ,  Tze Chan ,  Pradeep Ramachandramurthy Yelehanka

发明人： Jia Zheng ,  Weining Li ,  Tze Chan ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11 ,  H01L29/74

CPC分类号： H01L27/11 ,  H01L27/0617 ,  H01L29/66393 ,  H01L29/7436

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在其中形成沟槽。 在沟槽周围和半导体衬底内形成晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 晶闸管的栅极形成在沟槽内。 在半导体衬底上形成存取晶体管。 在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US20050098794A1

公开(公告)日：2005-05-12

申请号：US11009772

申请日：2004-12-11

申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423

CPC分类号： H01L29/66393 ,  H01L27/11

摘要： An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

摘要翻译： 集成电路结构包括形成在其上的半导体衬底和晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US20050079674A1

公开(公告)日：2005-04-14

申请号：US10683052

申请日：2003-10-09

申请人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

发明人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成栅介质层。 栅极电介质层在半导体衬底上的多个器件区域中形成多个厚度。 在至少一个器件区域上形成第二介电层。 在第二电介质层的至少一部分上形成第三电介质层。 然后在第二介电层的部分中选择性地注入离子阱。

公开(公告)号：US07964894B2

公开(公告)日：2011-06-21

申请号：US12784156

申请日：2010-05-20

申请人： Elgin Kiok Boone Quek ,  Pradeep Ramachandramurthy Yelehanka

发明人： Elgin Kiok Boone Quek ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L27/092

CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

摘要： An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.

摘要翻译： 一种集成电路系统，包括：衬底，其包括由间隔物限定的源极/漏极区域; 衬底上的一个门; 在栅极和衬底之间的栅极电介质; 栅极和源极/漏极区域内的再结晶区域; 以及表现出应力记忆特征的通道。

公开(公告)号：US20110237072A1

公开(公告)日：2011-09-29

申请号：US13158660

申请日：2011-06-13

申请人： Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

发明人： Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

IPC分类号： H01L21/768

CPC分类号： H01L21/823878 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.

摘要翻译： 一种集成电路系统的制造方法，包括：提供包括有源器件的衬底; 在所述衬底中形成穿硅通孔; 在穿通硅通孔上形成绝缘层，以保护穿硅通孔; 在形成绝缘层之后形成与有源器件的接触; 并去除绝缘层。

公开(公告)号：US07960282B2

公开(公告)日：2011-06-14

申请号：US12470028

申请日：2009-05-21

申请人： Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

发明人： Pradeep Ramachandramurthy Yelehanka ,  Denise Tan ,  Chung Meng Lek ,  Thomas Thiam ,  Jeffrey C. Lam ,  Liang-Choo Hsia

IPC分类号： H01L21/768

CPC分类号： H01L21/823878 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.

摘要翻译： 一种集成电路系统的制造方法，包括：提供包括有源器件的衬底; 在所述衬底中形成穿硅通孔; 在穿通硅通孔上形成绝缘层，以保护穿硅通孔; 在形成绝缘层之后形成与有源器件的接触; 并去除绝缘层。

公开(公告)号：US08513767B2

公开(公告)日：2013-08-20

申请号：US13052134

申请日：2011-03-21

申请人： Rama Krishna Kotlanka ,  Rakesh Kumar ,  Premachandran Chirayarikathuveedu Sankarapillai ,  Pradeep Ramachandramurthy Yelehanka

发明人： Rama Krishna Kotlanka ,  Rakesh Kumar ,  Premachandran Chirayarikathuveedu Sankarapillai ,  Pradeep Ramachandramurthy Yelehanka

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/76898 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

摘要： A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.

摘要翻译： 公开了一种用于形成装置的方法。 提供具有第一和第二主表面的支撑基板。 通过支撑衬底中的第一和第二主表面形成互连。 互连具有第一和第二部分。 第一部分从第一或第二主表面中的一个延伸，第二部分从第一和第二主表面中的另一个延伸。 互连包括在互连的第一部分中具有导电材料的部分通孔塞。 通孔塞在第一和第二部分的界面的大约一个界面处具有底部。 互连的第二部分用第一极性类型的掺杂剂重掺杂。