公开(公告)号：US20060284256A1

公开(公告)日：2006-12-21

申请号：US11157200

申请日：2005-06-17

Applicant: Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee

IPC: H01L23/62

CPC classification number: H01L27/0266

Abstract: The present invention provides a layout structure for an electrostatic discharge (ESD) protection circuit. The layout structure includes a first MOS device area, a second MOS device area, and a doped region. The first MOS device area has at least one source/drain region of a first polarity type. The second MOS device, which is adjacent to the first MOS device area, has at least one source/drain region of the first polarity type. A doped region of a second polarity type is interposed between the source/drain region of the first MOS device and the source/drain region of the second MOS device, such that the doped region and the source/drain regions interfacing therewith forming one or more diodes for dissipating ESD charges during an ESD event.

Abstract translation: 本发明提供了一种用于静电放电（ESD）保护电路的布局结构。 布局结构包括第一MOS器件区域，第二MOS器件区域和掺杂区域。 第一MOS器件区域具有至少一个第一极性类型的源极/漏极区域。 与第一MOS器件区域相邻的第二MOS器件具有至少一个第一极性类型的源极/漏极区域。 第二极性类型的掺杂区介于第一MOS器件的源极/漏极区域和第二MOS器件的源极/漏极区域之间，使得与其形成一个或多个的掺杂区域和源极/漏极区域 用于在ESD事件期间耗散ESD电荷的二极管。

公开(公告)号：US20060278928A1

公开(公告)日：2006-12-14

申请号：US11152440

申请日：2005-06-14

Applicant: Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Kuan-Lun Chang ,  Chuan-Ying Lee ,  Jian-Hsing Lee

IPC: H01L23/62

CPC classification number: H01L27/0262

Abstract: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.

Abstract translation: 公开了一种用于静电放电（ESD）保护电路的半导体布局结构。 半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流 触发可控硅整流器，以在ESD事件期间耗散ESD电荷。 第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。

公开(公告)号：US20060268474A1

公开(公告)日：2006-11-30

申请号：US11137265

申请日：2005-05-25

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee

IPC: H02H9/00

CPC classification number: H01L27/0251

Abstract: The present invention discloses a tie-off circuit coupled between a first potential and a gate of a MOS device whose source is connected to a second potential. The tie-off circuit includes at least one resistor and at least on diode. The resistor is coupled between the gate of the MOS device and the first potential for preventing the gate of the MOS device from floating during a normal circuit operation. The diode is coupled between the gate of the MOS device and the first potential, in parallel with the resistor, for reducing a voltage difference across a gate oxide layer of the MOS device during an electrostatic discharge (ESD) event, thereby protecting the same from ESD damage.

Abstract translation: 本发明公开了一种耦合在源极连接到第二电位的MOS器件的第一电位和栅极之间的断开电路。 连接电路至少包括一个电阻器，并且至少在二极管上。 电阻器耦合在MOS器件的栅极和用于防止MOS器件的栅极在正常电路操作期间浮置的第一电位之间。 二极管耦合在MOS器件的栅极和与电阻器并联的第一电位之间，用于在静电放电（ESD）事件期间减小MOS器件的栅氧化层上的电压差，从而保护 ESD损坏。

公开(公告)号：US06992361B2

公开(公告)日：2006-01-31

申请号：US10761658

申请日：2004-01-20

Applicant: Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shin ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L29/00

CPC classification number: H01L27/0921 ,  H01L21/823892 ,  H01L27/0928

Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

Abstract translation: CMOS半导体产品使用第一极性的第一掺杂阱和与第一极性相反的第二极性的第二掺杂阱，每个在半导体衬底内横向分离形成。 第一掺杂阱进一步嵌入在第二极性的第三掺杂阱中，其进一步将第一掺杂阱与第二掺杂阱分离。 第三掺杂阱为形成在第一掺杂阱和第二掺杂阱内的一对MOS晶体管提供闩锁电阻。

公开(公告)号：US20050280091A1

公开(公告)日：2005-12-22

申请号：US10887793

申请日：2004-07-09

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/08 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0814 ,  H01L29/0619

Abstract: A semiconductor integrated circuit structure includes a plurality of diodes disposed in the substrate. These diodes are electrically coupled in series. At least one insertion region is disposed in the substrate between two of the diodes and a supply voltage node electrically coupled to the insertion region. Preferably, a guard ring surrounds the diodes.

Abstract translation: 半导体集成电路结构包括设置在基板中的多个二极管。 这些二极管串联电耦合。 至少一个插入区域设置在两个二极管之间的衬底中，以及电耦合到插入区域的电源电压节点。 优选地，保护环围绕二极管。

公开(公告)号：US20050275987A1

公开(公告)日：2005-12-15

申请号：US10867112

申请日：2004-06-14

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L27/02 ,  H02H3/20 ,  H03K17/0814

CPC classification number: H03K17/08142 ,  H01L27/0266

Abstract: An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

Abstract translation: 提出了一种静电放电（ESD）保护电路及其方法。 在一些实施例中，高耐压输入/输出电路包括ESD检测电路，第一第一型晶体管，第一第二型晶体管和第二第二型晶体管。 第一第一型晶体管和第一第二型晶体管耦合到焊盘。 ESD检测电路确定ESD是否发生在焊盘处，如果是，则将第一和第二第二型晶体管的栅极耦合到第二电源轨。

公开(公告)号：US20050274990A1

公开(公告)日：2005-12-15

申请号：US10820320

申请日：2004-06-08

Applicant: Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/768 ,  H03K5/08

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

公开(公告)号：US06960811B2

公开(公告)日：2005-11-01

申请号：US10929735

申请日：2004-08-30

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0266

Abstract: A low capacitance ESD protection device. The device comprises a substrate, a well of a first conductivity type in the substrate, a first and second transistor of the first conductivity type respectively on two sides of the well, a guard ring of a second conductivity type in the substrate, surrounding the well, and the first and second transistor, and a doped region of the second conductivity type in the well, wherein profiles of a drain and source region of each of the first and second transistor are un-symmetrical, and an area of the drain region is smaller than that of the source region in each of the first and second transistor.

Abstract translation: 低电容ESD保护器件。 该器件包括衬底，衬底中的第一导电类型的阱，分别在阱的两侧上的第一导电类型的第一和第二晶体管，衬底中的第二导电类型的保护环，围绕阱 以及所述第一和第二晶体管以及所述阱中的所述第二导电类型的掺杂区域，其中所述第一和第二晶体管中的每一个的漏极和源极区域的轮廓是不对称的，并且所述漏极区域的面积为 小于第一和第二晶体管中的每一个中的源极区域。

公开(公告)号：US20050180071A1

公开(公告)日：2005-08-18

申请号：US10779341

申请日：2004-02-13

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongehen Ong

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Tongehen Ong

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0266 ,  H01L27/0288

Abstract: A circuit and a method for ESD protection are disclosed. The circuit includes an ESD protection circuit coupled to a pad. A device is coupled to the pad and an internal circuit. The device generates a voltage drop between the pad and the internal circuit, protecting thin oxide layers of the internal circuit from damage. The method comprises coupling an internal circuit to an ESD protection circuit and generating a voltage drop between a pad and the internal circuit to protect thin oxide layers of the internal circuit from damage when an ESD pulse is coupled to the pad.

Abstract translation: 公开了一种用于ESD保护的电路和方法。 电路包括耦合到焊盘的ESD保护电路。 器件耦合到焊盘和内部电路。 该器件在焊盘和内部电路之间产生电压降，保护内部电路的薄氧化物层免受损坏。 该方法包括将内部电路耦合到ESD保护电路并且在衬垫和内部电路之间产生电压降，以在ESD脉冲耦合到衬垫时保护内部电路的薄氧化物层免受损坏。

公开(公告)号：US20050176195A1

公开(公告)日：2005-08-11

申请号：US11072014

申请日：2005-03-04

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01G4/228 ,  H01G4/35 ,  H01L21/8234 ,  H01L23/60 ,  H02H9/00

CPC classification number: H01L27/0251

Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.