公开(公告)号：US08912567B2

公开(公告)日：2014-12-16

申请号：US12852995

申请日：2010-08-09

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US08211761B2

公开(公告)日：2012-07-03

申请号：US11465005

申请日：2006-08-16

申请人： Shyue Seng Tan ,  Yung Fu Chong ,  Lee Wee Teo

发明人： Shyue Seng Tan ,  Yung Fu Chong ,  Lee Wee Teo

IPC分类号： H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78618 ,  H01L29/78684

摘要： A semiconductor method includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions by forming an oxide layer over the silicon-germanium layer. An interlevel dielectric layer is formed over the gate and the source/drain regions. A plurality of contacts is formed in the interlevel dielectric layer to the gate and the plurality of source/drain regions.

摘要翻译： 半导体方法包括提供硅半导体衬底。 在硅半导体衬底上形成栅极和多个源/漏区，以形成至少一个pFET。 在多个源极/漏极区域上形成硅 - 锗层。 通过在硅 - 锗层上形成氧化物层，锗从硅 - 锗层冷凝以在多个源极/漏极区中形成多个源极/漏极。 在栅极和源极/漏极区域上形成层间电介质层。 在层间电介质层中形成多个触点到栅极和多个源极/漏极区域。

公开(公告)号：US20080286916A1

公开(公告)日：2008-11-20

申请号：US12179042

申请日：2008-07-24

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Brian L. Tessier

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Brian L. Tessier

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845

摘要： Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric.

摘要翻译： 公开了用替换的栅极和相关结构来施加晶体管的沟道的方法。 一种方法可以包括在包括其栅极的晶体管上提供固有应力的材料; 在门上移除一部分本征应力材料; 去除栅极的至少一部分，允许由栅极保持的应力传递到通道; 用更换的门更换（或补充）门; 并去除本征应力材料。 拆卸和更换门允许原始闸门保持的应力传递到通道，替换闸门保持（记住）这种情况。 这些方法不会损坏栅极电介质。

公开(公告)号：US20080116482A1

公开(公告)日：2008-05-22

申请号：US11561982

申请日：2006-11-21

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

IPC分类号： H01L27/092 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78639

摘要： Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

摘要翻译： 通过在源极/漏极区域或沟道区域之下形成应力区域并且在应力区域上使用横向外延形成选择性应变Si，从而在通道区域上具有应力的FET器件的实施例。 在第一示例性实施例中，在FET的沟道区之下的应力区域上形成横向外延层。 在第二示例性实施例中，在FET的源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在第三示例性实施例中，形成PFET和NFET器件。 在PFET器件中，在源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在NFET器件中，横向外延层形成在NFET的沟道区下方的应力区域上。

公开(公告)号：US20080042209A1

公开(公告)日：2008-02-21

申请号：US11465005

申请日：2006-08-16

申请人： Shyue Seng Tan ,  Yung Fu Chong ,  Lee Wee Teo

发明人： Shyue Seng Tan ,  Yung Fu Chong ,  Lee Wee Teo

IPC分类号： H01L29/94

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78618 ,  H01L29/78684

摘要： A semiconductor system includes providing a silicon semiconductor substrate. A gate and a plurality of source/drain regions are formed on the silicon semiconductor substrate to form at least one pFET. A silicon-germanium layer is formed over the plurality of source/drain regions. The germanium is condensed from the silicon-germanium layer to form a plurality of source/drains in the plurality of source/drain regions. An interlevel dielectric layer is formed over the gate and the source/drain regions. A plurality of contacts is formed in the interlevel dielectric layer to the gate and the plurality of source/drain regions.

摘要翻译： 半导体系统包括提供硅半导体衬底。 在硅半导体衬底上形成栅极和多个源/漏区，以形成至少一个pFET。 在多个源极/漏极区域上形成硅 - 锗层。 锗从硅 - 锗层冷凝，以在多个源极/漏极区域中形成多个源极/漏极。 在栅极和源极/漏极区域上形成层间电介质层。 在层间电介质层中形成多个触点到栅极和多个源极/漏极区域。

公开(公告)号：US20070267703A1

公开(公告)日：2007-11-22

申请号：US11383951

申请日：2006-05-17

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/94

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US06624489B2

公开(公告)日：2003-09-23

申请号：US10033284

申请日：2001-12-31

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L2976

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

公开(公告)号：US06534390B1

公开(公告)日：2003-03-18

申请号：US10050444

申请日：2002-01-16

申请人： Yung Fu Chong ,  Randall Cha ,  Kin Leong Pey

发明人： Yung Fu Chong ,  Randall Cha ,  Kin Leong Pey

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/3212 ,  H01L29/41783 ,  H01L29/66545

摘要： The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

摘要翻译： 本发明提供一种硅/非晶硅/金属结构（SASM）的改进的半导体器件以及通过使用退火在硅源/漏区上形成厚硅化物膜而通过自对准硅化物工艺制造改进的半导体器件的方法， 然后执行化学机械抛光（CMP）步骤以在栅极处去除间隔物的顶部上的硅化物，从而破坏从栅极延伸到源极漏极区的硅化物膜的连续性。

公开(公告)号：US08643119B2

公开(公告)日：2014-02-04

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.

摘要翻译： 根据实施例的用于半导体器件的结构包括：基本上L形的硅化物元件，其包括基底构件和延伸构件，其中所述基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得 基部构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。

公开(公告)号：US08450775B2

公开(公告)日：2013-05-28

申请号：US13229773

申请日：2011-09-12

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

IPC分类号： H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

摘要翻译： 应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。 另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。