公开(公告)号：US06624489B2

公开(公告)日：2003-09-23

申请号：US10033284

申请日：2001-12-31

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L2976

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

公开(公告)号：US06391731B1

公开(公告)日：2002-05-21

申请号：US09784251

申请日：2001-02-15

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the exposed semiconductor substrate to form a deep amorphous layer. Ions are implanted into the deep amorphous layer to form pre-annealed source and drain junctions. The temporary sidewall spacers are removed. Ions are implanted into the exposed semiconductor substrate to form a shallow amorphous layer. Ions are implanted into the shallow amorphous layer to form pre-annealed source and drain extensions. A capping layer may be deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation. The semiconductor substrate is irradiated with laser light to melt the amorphous layer while the crystalline regions of the semiconductor substrate remain in solid state. Ions in the pre-annealed source and drain junctions diffuse in the deep amorphous layer while ions in the pre-annealed source and drain extensions diffuse into the shallower amorphous layer. The source and drain junctions and the source and drain extensions for the transistors are thereby simultaneously formed.

摘要翻译： 已经实现了在集成电路器件的制造中形成具有浅源极和漏极延伸以及深源极和漏极结的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到暴露的半导体衬底中以形成深非晶层。 将离子注入到深非晶层中以形成预退火的源极和漏极结。 移除临时侧壁间隔物。 将离子注入到暴露的半导体衬底中以形成浅的非晶层。 将离子注入到浅非晶层中以形成预退火的源极和漏极延伸。 覆盖半导体衬底和栅极的覆盖层可以沉积，以在照射期间保护半导体衬底。 半导体衬底用激光照射以熔化非晶层，同时半导体衬底的结晶区保持固态。 预退火源极和漏极结中的离子在深非晶层中扩散，而预退火的源极和漏极延伸部中的离子扩散到较浅的非晶层中。 从而同时形成晶体管的源极和漏极结以及源极和漏极延伸。

公开(公告)号：US06365446B1

公开(公告)日：2002-04-02

申请号：US09609751

申请日：2000-07-03

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

摘要翻译： 一种用于制造具有深源极/漏极结的MOS型晶体管和具有期望的界面和电学性质的薄的硅化物触点的方法。 这些器件通过一种方法产生，该方法涉及通过离子注入，栅极，源极和漏极区域的非晶化，金属层的形成，通过金属层的离子注入，形成覆盖层和随后的激光退火 。

公开(公告)号：US06335253B1

公开(公告)日：2002-01-01

申请号：US09614557

申请日：2000-07-12

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

IPC分类号： H01L21336

CPC分类号： H01L21/268 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the semiconductor substrate and the polysilicon layer to form deep amorphous layers beside the spacers and shallow amorphous layers under the spacers. The spacers are removed. Ions are implanted to form lightly doped junctions in the shallower amorphous layer. Permanent sidewall spacers are formed on the gates. Ions are implanted to form heavily doped junctions in the deeper amorphous layer. A metal layer is deposited. A capping layer is deposited to protect the metal layer during irradiation. The integrated circuit device is irradiated with laser light to melt the amorphous layer while the crystalline polysilicon and semiconductor substrate remain in solid state. The metal layer is heated, and may be melted, to cause reaction with the silicon to form silicide. Ions in the heavily doped junctions and in the lightly doped junctions are also thereby diffused into the amorphous layer. The deep source and drain junctions, the shallow source and drain extensions, and a silicide layer are simultaneously formed. A heat treatment crystallizes the silicide to improve resistivity.

摘要翻译： 已经实现了一种形成具有浅源极和漏极延伸和自对准硅化物的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到半导体衬底和多晶硅层中，以在间隔物旁边的隔离层和浅非晶层之间形成深非晶层。 去除间隔物。 在较浅的非晶层中植入离子以形成轻掺杂的结。 在门上形成永久侧壁间隔物。 植入离子以在较深的非晶层中形成重掺杂的结。 沉积金属层。 沉积覆盖层以在照射期间保护金属层。 用激光照射集成电路器件以熔化非晶层，同时晶体多晶硅和半导体衬底保持固态。 金属层被加热并且可能被熔化，从而与硅反应形成硅化物。 在重掺杂结和轻掺杂结中的离子也因此扩散到非晶层中。 同时形成深源极和漏极结，浅源极和漏极延伸部分以及硅化物层。 热处理使硅化物结晶以提高电阻率。

公开(公告)号：US06890854B2

公开(公告)日：2005-05-10

申请号：US09726903

申请日：2000-11-29

申请人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

发明人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L21/26

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

摘要翻译： 公开了一种用于进行镍盐化的方法和装置。 镍硅化物工艺通常包括：形成包括部分制造的集成电路部件和硅衬底的处理衬底; 将氮气掺入经处理的基底中; 将镍沉积在经处理的基底上; 对经处理的基板退火以形成单一硅化镍; 去除未反应的镍; 并执行串联程序来完成集成电路制造。 该镍硅化物工艺增加了退火温度范围，通过盐化可在硅上形成连续的薄镍单硅化物层。 它还延迟了单一硅化镍薄膜的聚集开始到更高的退火温度。 此外，该镍硅化物工艺延迟了从单一硅化镍到更高电阻率的二硅化镍的转变到更高的退火温度。 它还减少了镍增强的多晶硅晶粒生长，以防止层反转。 这种镍硅化物工艺的一些实施例可以用于另外标准的自对准硅化物工艺中，以形成具有低电阻率晶体管栅电极和源极/漏极接触的集成电路器件。

公开(公告)号：US09318378B2

公开(公告)日：2016-04-19

申请号：US10923123

申请日：2004-08-21

申请人： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

发明人： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

公开(公告)号：US07030451B2

公开(公告)日：2006-04-18

申请号：US11081908

申请日：2005-03-15

申请人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

发明人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US06734072B1

公开(公告)日：2004-05-11

申请号：US10379814

申请日：2003-03-05

申请人： Yung Fu Chong ,  Alex See

发明人： Yung Fu Chong ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606

摘要： A method of forming a conductive gate structure on an underlying gate insulator layer, without the use of a plasma dry etch conductive gate definition procedure, has been developed. After formation of source/drain extension (SDE) and heavily doped source/drain regions, an opening is formed in a planarized dielectric layer exposing the top surface of a semiconductor alloy layer, or exposing the top surface of a semiconductor substrate, while the planarized dielectric layer and adjacent insulator spacers overlay the source/drain regions. A multiple spike, rapid thermal oxidation (RTO) procedure is employed to grow a gate insulator layer on the region of semiconductor alloy, or semiconductor, exposed in the opening, with the low temperature RTO procedure, and the planarized dielectric layer overlying the source/drain regions, suppressing out diffusion of SDE dopants. A conductive layer is next deposited and then planarized via a chemical mechanical polishing procedure, resulting in the definition of a conductive gate structure on the gate insulator layer, with the conductive gate structure formed without employment of plasma dry etching eliminating the risk of plasma induced damage of the gate insulator layer.

摘要翻译： 已经开发了在下面的栅极绝缘体层上形成导电栅极结构的方法，而不使用等离子体干蚀刻导电栅极定义程序。 在形成源极/漏极延伸（SDE）和重掺杂源极/漏极区之后，在平坦化介电层中形成开口，暴露半导体合金层的顶表面，或暴露半导体衬底的顶表面，同时平坦化 电介质层和相邻的绝缘体间隔物覆盖源极/漏极区域。 采用多重峰值快速热氧化（RTO）方法，在半导体合金或半导体区域中，在低温RTO工艺下，在开口部分暴露的半导体区域上生长栅极绝缘体层，并且覆盖源极/ 漏区，抑制SDE掺杂物的扩散。 接着沉积导电层，然后通过化学机械抛光程序平坦化，导致栅极绝缘体层上的导电栅极结构的定义，导电栅极结构形成而不需要等离子体干蚀刻，消除了等离子体诱发损伤的风险 的栅极绝缘体层。

公开(公告)号：US06727151B2

公开(公告)日：2004-04-27

申请号：US10213562

申请日：2002-08-07

申请人： Yung Fu Chong ,  Randall Cher Liang Cha ,  Alex See

发明人： Yung Fu Chong ,  Randall Cher Liang Cha ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7834

摘要： A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening. The gate material layer, first polysilicon spacers and second polysilicon spacers are polished back to the polish stop layer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种形成具有升高的源极/漏极结构的MOSFET的方法。 牺牲氧化物层设置在基板上。 抛光停止层沉积在牺牲氧化物层上。 沉积在抛光停止层上的氧化物层。 通过氧化物层和抛光停止层形成到牺牲氧化物层的开口。 第一多晶硅间隔物形成在开口的侧壁上，其中第一多晶硅间隔物形成升高的源极/漏极结构。 在第一多晶硅间隔物上形成第二多晶硅间隔物。 去除暴露在开口内的氧化物层和牺牲氧化物层。 在开口内生长外延硅层。 在覆盖第二多晶硅间隔物和外延硅层的开口内形成栅介质层。 栅极材料层沉积在开口内。 栅极材料层，第一多晶硅间隔物和第二多晶硅间隔物被抛光回到抛光停止层，从而在集成电路器件的制造中完成形成具有升高的源极/漏极结构的MOSFET。

公开(公告)号：US20070293039A1

公开(公告)日：2007-12-20

申请号：US11454397

申请日：2006-06-16

申请人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

摘要翻译： 公开了一种在电介质层中填充间隙的方法。 提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。 形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。 用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。 然后使用ECP来完成间隙的铜填充。 对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。