公开(公告)号：US20100327371A1

公开(公告)日：2010-12-30

申请号：US12805962

申请日：2010-08-26

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US5877980A

公开(公告)日：1999-03-02

申请号：US824483

申请日：1997-03-26

申请人： Kyong-moo Mang ,  Jung-dal Choi

发明人： Kyong-moo Mang ,  Jung-dal Choi

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.

摘要翻译： 一种在非易失性存储单元上形成导电“程序辅助板”的非易失性存储器件。 对程序辅助板施加适当的电压以大大增加单元耦合比，从而减少编程和擦除电压，并提高操作速度。 制造过程简单，并且其导致更平坦的结构，其有助于后续制造工艺。

公开(公告)号：US5671176A

公开(公告)日：1997-09-23

申请号：US715077

申请日：1996-09-19

申请人： Dong-soo Jang ,  Jung-dal Choi

发明人： Dong-soo Jang ,  Jung-dal Choi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/10

摘要： An integrated circuit memory device includes a plurality of wordlines, a plurality of program inhibition lines, a plurality of serially connected memory cell transistors, and a plurality of program inhibition capacitors. Each of the memory cell transistors includes a gate connected to a respective one of the wordlines. Each of the program inhibition capacitors has a first terminal connected to a source/drain of a respective one of the memory cell transistors, and a second terminal connected to a respective one of the program inhibition lines. Related methods are also disclosed.

摘要翻译： 集成电路存储器件包括多个字线，多个编程禁止线，多个串联的存储单元晶体管和多个编程禁止电容器。 每个存储单元晶体管包括连接到字线中相应一个的栅极。 每个编程禁止电容器具有连接到存储单元晶体管的相应一个的源极/漏极的第一端子和连接到相应的一个编程禁止线路的第二端子。 还公开了相关方法。

公开(公告)号：US20160104705A1

公开(公告)日：2016-04-14

申请号：US14754400

申请日：2015-06-29

申请人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

发明人： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

IPC分类号： H01L27/088 ,  H01L27/12

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211

摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

摘要翻译： 半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。 逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。 第一和第二栅极电介质层具有不同的厚度。 还讨论了相关设备和制造方法。

公开(公告)号：US20080135912A1

公开(公告)日：2008-06-12

申请号：US11976389

申请日：2007-10-24

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

摘要翻译： 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US08765572B2

公开(公告)日：2014-07-01

申请号：US13168312

申请日：2011-06-24

申请人： Yong-lack Choi ,  Chang-hyun Cho ,  Seung-pil Chung ,  Hyun-seok Jang ,  Du-heon Song ,  Jung-dal Choi

发明人： Yong-lack Choi ,  Chang-hyun Cho ,  Seung-pil Chung ,  Hyun-seok Jang ,  Du-heon Song ,  Jung-dal Choi

IPC分类号： H01L21/764

CPC分类号： H01L21/7682 ,  H01L27/11521 ,  H01L27/11526

摘要： A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.

摘要翻译： 一种制造半导体器件的方法，其中字线之间的干涉效应被显着地减少或消除，包括在衬底上形成多个栅极图案; 在所述栅极图案之间形成第一绝缘层，所述第一绝缘层填充所述栅极图案之间的区域; 蚀刻第一绝缘层以将第一绝缘层的一部分去除到预定深度; 以及在栅极图案和第一绝缘层上形成第二绝缘层。 在栅极图案之间形成低介电常数材料。

公开(公告)号：US20110260237A1

公开(公告)日：2011-10-27

申请号：US13042051

申请日：2011-03-07

申请人： Jae-goo Lee ,  Jung-dal Choi ,  Young-woo Park

发明人： Jae-goo Lee ,  Jung-dal Choi ,  Young-woo Park

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.

摘要翻译： 存储器件包括衬底，从衬底垂直延伸的半导体柱和沿着半导体柱的侧壁设置的多个间隔开的电荷存储单元。 每个存储单元包括设置在半导体柱的侧壁上的隧道绝缘层，设置在隧道绝缘层上的聚合物层，设置在聚合物层上或其中的多个量子点以及设置在聚合物上的阻挡绝缘层 层。

公开(公告)号：US07808036B2

公开(公告)日：2010-10-05

申请号：US11976389

申请日：2007-10-24

申请人： Chang-Hyun Lee ,  Jung-dal Choi

发明人： Chang-Hyun Lee ,  Jung-dal Choi

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

公开(公告)号：US6093605A

公开(公告)日：2000-07-25

申请号：US199312

申请日：1998-11-25

申请人： Kyong-moo Mang ,  Jung-dal Choi

发明人： Kyong-moo Mang ,  Jung-dal Choi

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device in which an electrically conductive "program assist plate" is formed over the nonvolatile memory cells. Appropriate voltages are applied to the program assist plate to greatly increase the cell coupling ratio, thereby reducing the program and erase voltages, and increasing the speed of operation. The manufacturing process is simple, and it results in a more planar structure which facilitates subsequent manufacturing processes.

摘要翻译： 一种在非易失性存储单元上形成导电“程序辅助板”的非易失性存储器件。 对程序辅助板施加适当的电压以大大增加单元耦合比，从而减少编程和擦除电压，并提高操作速度。 制造过程简单，并且其导致更平坦的结构，其有助于后续制造工艺。

公开(公告)号：US5734609A

公开(公告)日：1998-03-31

申请号：US757266

申请日：1996-11-29

申请人： Jung-dal Choi ,  Dong-Jun Kim

发明人： Jung-dal Choi ,  Dong-Jun Kim

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/0483

摘要： Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.

摘要翻译： 具有降低的对无意编程和擦除的敏感性的集成电路存储器件包括布置成共享共同控制线（例如，SSL1，SSL2）和字线（例如，WL1-WLn）的多个EEPROM单元的NAND串的存储器单元的阵列， 。 这些NAND串优选地包括具有第一和第二端的线性阵列或EEPROM单元串，以及分别连接（直接或间接）到其第一和第二端的第一和第二选择晶体管（ST1，ST2），以提供改进的程序和 擦除能力，反并联提供一对NAND串并共享一个公共位线，但是这对NAND串形成在衬底中的各个非重叠阱区中，使得各个NAND串中的EEPROM单元的沟道区可以 分别控制（例如，升高）以防止在相邻串中的单元被编程或擦除时意外编程或擦除。