公开(公告)号：US20120068870A1

公开(公告)日：2012-03-22

申请号：US12887327

申请日：2010-09-21

申请人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song

发明人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song

IPC分类号： H03M1/12

CPC分类号： H03M1/06 ,  H03M1/12

摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括模数转换器电路，数字滤波器电路，数据检测器电路，模拟滤波器电路和采样时钟产生电路的数据处理电路。 模数转换器电路可操作以接收数据输入并提供对应的数字采样。 数字滤波器电路可操作以接收数字样本并提供滤波输出。 数据检测器电路可操作以对滤波的输出执行数据检测处理，以产生检测的输出。 模拟滤波器电路可操作以接收数字样本并提供模拟输出。 采样时钟产生电路可操作以至少部分地基于所检测的输出和模拟输出来提供采样时钟。

公开(公告)号：US20110075718A1

公开(公告)日：2011-03-31

申请号：US12570326

申请日：2009-09-30

申请人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song ,  Lingyan Sun

发明人： Jingfeng Liu ,  Haotian Zhang ,  Hongwei Song ,  Lingyan Sun

IPC分类号： H04L27/01

CPC分类号： G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10481 ,  H03H17/0294

摘要： In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

摘要翻译： 在一个实施例中，（硬盘驱动器）读通道具有（DFIR均衡）滤波器，其抽头系数被自适应地更新。 复位控制器监视在滤波器下游产生的（LLR）信号，以自动确定何时复位滤波器，例如通过重新加载用户指定的抽头系数的初始集合。 对于LLR值，当复位控制器检测到过多的近期LLR值具有太低的置信度值时，复位控制器确定复位滤波器。 当在硬盘驱动器读取通道中实现时，复位控制器可以在硬盘驱动器的扇区内的读取操作期间复位一次或多次过滤器。

公开(公告)号：US08537883B1

公开(公告)日：2013-09-17

申请号：US13365712

申请日：2012-02-03

申请人： Jingfeng Liu ,  Hongwei Song ,  Jin Xie

发明人： Jingfeng Liu ,  Hongwei Song ,  Jin Xie

IPC分类号： H03H7/30

CPC分类号： G11B20/10351 ,  G11B20/10046 ,  G11B20/10296 ,  G11B2220/2537 ,  H04L1/0054 ,  H04L25/03038 ,  H04L27/0014 ,  H04L2027/003 ,  H04L2027/0038

摘要： A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

摘要翻译： 一种用于从数字信号中去除低频偏移失真的系统，该系统包括用于将与光学存储介质相关联的模拟频率信号转换为数字频率信号的模拟 - 数字转换器; 均衡器以均衡数字频率信号; 用于估计数字频率信号的低频偏移失真的估计器; 补偿器，用于使用所述估计从所述均衡数字频率信号基本上消除所述数字频率信号的低频偏移失真; 以及解码器，用于解码具有基本上从其中抵消的低频偏移失真的均衡数字频率信号。

公开(公告)号：US08266505B2

公开(公告)日：2012-09-11

申请号：US12540283

申请日：2009-08-12

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H03M13/00

CPC分类号： G06F3/05 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/27 ,  H03M13/3905 ,  H03M13/41 ,  H03M13/47 ,  H03M13/63 ,  H03M13/6331

摘要： Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples.

摘要翻译： 本发明的各种实施例提供了用于数据处理系统的系统和方法。 作为一个示例，描述了包括模数转换器，在线定时循环和离线定时循环的数据处理电路。 模数转换器接收模拟输入并提供第一系列数据样本第一系列数据采样的每一位对应于在更新的采样时钟控制的时间的模拟输入。 在线定时循环至少部分地基于第一系列数据样本的处理版本来修改更新的采样时钟。 离线时序循环内插第一系列数据样本的导数，以产生模拟与使用自由运行时钟采样的模拟输入相对应的一系列数据样本的第二系列数据采样。 根据在第二系列数据样本中显示的平均频率偏移，内插第二系列数据样本以调整每个位。

公开(公告)号：US20110298543A1

公开(公告)日：2011-12-08

申请号：US12792555

申请日：2010-06-02

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： H03G3/20

CPC分类号： G11B20/10009 ,  G11B20/10027 ,  G11B20/10462 ,  G11B2020/1287 ,  G11B2220/2516 ,  H03G1/0088

摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，本发明的一些实施例提供包括可变增益放大器，增益电路和混合增益反馈组合电路的数据处理电路。 可变增益放大器可操作以将增益应用于对应于增益反馈值的数据输入并提供放大的输出。 增益电路可操作以至少部分地基于放大的输出来计算第一算法误差分量和第二算法误差分量。 当数据输入包括同步模式时，混合增益反馈组合电路可操作地组合第一算法误差分量和第二算法误差分量以产生增益反馈值。

公开(公告)号：US20100083075A1

公开(公告)日：2010-04-01

申请号：US12241919

申请日：2008-09-30

申请人： Jingfeng Liu ,  Shaohua Yang ,  Hongwei Song ,  Yuan Xing Lee

发明人： Jingfeng Liu ,  Shaohua Yang ,  Hongwei Song ,  Yuan Xing Lee

IPC分类号： H03M13/05 ,  G06F11/14

CPC分类号： G11B20/18 ,  G11B2020/183 ,  G11B2220/2516 ,  H03M13/1105 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/6343

摘要： Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

摘要翻译： 提供了用于改进硬盘驱动器中物理重读操作的方法和装置。 所公开的方法和设备选择性地将数据保留在硬盘驱动器中。 通过将读取信号中的多个段中的每一个分配可靠度度量，在迭代读取通道中读取信号; 重复多个读取操作的分配步骤; 并且基于所分配的可靠性度量选择性地保留段。 可以通过将传感器定位在存储介质上来获得读取信号。 可靠性度量可以基于软比特决策; 对数似然比或给定段的噪声估计。

公开(公告)号：US08441751B1

公开(公告)日：2013-05-14

申请号：US11840682

申请日：2007-08-17

申请人： Hongwei Song ,  Zining Wu ,  Jingfeng Liu ,  Toai Doan

发明人： Hongwei Song ,  Zining Wu ,  Jingfeng Liu ,  Toai Doan

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10222 ,  G11B2220/2516

摘要： A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, a symbol timing loop and read circuit, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device without disturbing the symbol timing loop and read circuit.

摘要翻译： 接收设备可以被配置为使用在接收设备的基本读取的信道符号率处采样的符号来导出过采样的双位脉冲响应估计。 接收设备可以包括数据获取电路，其被配置为数字化从存储介质导出的数据，符号定时循环和读取电路，以及配置为使用在读取通道上采样的符号来估计过采样双位脉冲响应的双位脉冲估计电路 接收设备的速率，而不会干扰符号定时循环和读取电路。

公开(公告)号：US08312359B2

公开(公告)日：2012-11-13

申请号：US12562200

申请日：2009-09-18

申请人： Jingfeng Liu ,  Hongwei Song ,  Lingyan Sun

发明人： Jingfeng Liu ,  Hongwei Song ,  Lingyan Sun

IPC分类号： H03M13/03 ,  G06F11/00

CPC分类号： H03M13/1102 ,  H03M13/296 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6343

摘要： In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets of four hard-decision bits, (ii) the noise estimate, and (iii) bandwidth values. The bandwidth values for at least two of the two or more update blocks are selected such that they are different from one another. Selecting different bandwidth values may reduce the bit-error rate for the receiver over the bit-error rate that may be achieved by selecting the bandwidth values to be the same as one another.

摘要翻译： 在一个实施例中，信号处理接收机具有分支量测校准（BMC）单元，其接收（i）来自信道检测器的四个硬判决位的集合，以及（ii）噪声估计。 BMC单元具有两个或多个更新块（例如抽头重量更新和/或偏置补偿块），其生成由信道检测器的分支度量单元使用的更新参数以改善信道检测。 两个或多个更新块基于（i）四个硬判决位的集合，（ii）噪声估计和（iii）带宽值）来生成更新的参数。 选择两个或多个更新块中的至少两个的带宽值使得它们彼此不同。 选择不同的带宽值可以通过选择彼此相同的带宽值来实现的比特错误率降低接收机的比特误码率。

公开(公告)号：US08225183B2

公开(公告)日：2012-07-17

申请号：US12241919

申请日：2008-09-30

申请人： Jingfeng Liu ,  Shaohua Yang ,  Hongwei Song ,  Yuan Xing Lee

发明人： Jingfeng Liu ,  Shaohua Yang ,  Hongwei Song ,  Yuan Xing Lee

IPC分类号： H03M13/00

CPC分类号： G11B20/18 ,  G11B2020/183 ,  G11B2220/2516 ,  H03M13/1105 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/6343

摘要： Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

摘要翻译： 提供了用于改进硬盘驱动器中物理重读操作的方法和装置。 所公开的方法和设备选择性地将数据保留在硬盘驱动器中。 通过将读取信号中的多个段中的每一个分配可靠度度量，在迭代读取通道中读取信号; 重复多个读取操作的分配步骤; 并且基于所分配的可靠性度量选择性地保留段。 可以通过将传感器定位在存储介质上来获得读取信号。 可靠性度量可以基于软比特决策; 对数似然比或给定段的噪声估计。

公开(公告)号：US08675298B2

公开(公告)日：2014-03-18

申请号：US12992933

申请日：2009-01-09

申请人： Jingfeng Liu ,  Hongwei Song

发明人： Jingfeng Liu ,  Hongwei Song

IPC分类号： G11B5/035 ,  G11B20/10

CPC分类号： G11B20/10009 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10046 ,  G11B20/10212 ,  G11B20/10481 ,  G11B2220/2516

摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，本发明的一些实施例提供了包括主数据处理电路和自适应设置确定电路的数据处理电路。 主数据处理电路接收一系列数据样本，包括：均衡器电路和数据检测器电路。 均衡器电路接收一系列数据样本并提供均衡的输出。 均衡器电路至少部分地由系数控制。 数据检测器电路接收均衡器输出并且至少部分地基于目标提供主数据输出。 自适应设置确定电路接收一系列数据样本和主数据输出，并与主数据处理电路并行操作，以自适应地确定系数和目标。