公开(公告)号：US20050093100A1

公开(公告)日：2005-05-05

申请号：US10700085

申请日：2003-11-03

申请人： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L31/117

CPC分类号： H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

摘要翻译： 提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。 在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

公开(公告)号：US20100006985A1

公开(公告)日：2010-01-14

申请号：US12170459

申请日：2008-07-10

申请人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

发明人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/76245

摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.

摘要翻译： 提供了一种制造绝缘体上硅衬底的方法。 这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。 随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。 上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。 然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层 从底层半导体区域。 可以在非高p型掺杂外延层同时退火的同时执行这种处理。

公开(公告)号：US20070235759A1

公开(公告)日：2007-10-11

申请号：US11401672

申请日：2006-04-11

申请人： William Henson ,  Yaocheng Liu ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana

发明人： William Henson ,  Yaocheng Liu ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana

IPC分类号： H01L31/00

CPC分类号： H01L21/2807 ,  H01L21/823842

摘要： An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.

摘要翻译： 提供了用于在同一半导体衬底上为pFET器件提供nFET器件的Si栅极和SiGe栅极的集成方案。 该集成方案包括首先提供材料堆叠，其从底部到顶部包括在半导体衬底的表面上的栅极电介质，Si膜和硬掩模，其包括至少一个nFET器件区域和至少一个pFET器件区域 。 接下来，将硬掩模从至少一个pFET器件区域中的材料堆叠中选择性地去除，从而暴露Si膜。 暴露的Si膜然后被转换成SiGe膜，此后在至少一个nFET器件区域中形成至少一个nFET器件，并且在至少一个pFET器件区域中形成至少一个pFET器件。 根据本发明，至少一个nFET器件包括Si栅极，并且至少一个pFET包括SiGe栅极。

公开(公告)号：US07772096B2

公开(公告)日：2010-08-10

申请号：US12170459

申请日：2008-07-10

申请人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

发明人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76245

摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.

摘要翻译： 提供了一种制造绝缘体上硅衬底的方法。 这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。 随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。 上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。 然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层 从底层半导体区域。 可以在非高p型掺杂外延层同时退火的同时执行这种处理。

公开(公告)号：US20070238276A1

公开(公告)日：2007-10-11

申请号：US11402177

申请日：2006-04-11

申请人： Yaocheng Liu ,  Alexander Reznicek ,  Devendra Sadana

发明人： Yaocheng Liu ,  Alexander Reznicek ,  Devendra Sadana

IPC分类号： H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/28035 ,  H01L21/32155 ,  H01L29/4916

摘要： A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein.

摘要翻译： 提供了一种利用气相掺杂工艺在CMOS结构中控制多晶硅耗尽效应的方法，该方法能够在栅极电介质/多晶硅界面处提供高浓度的掺杂剂原子。 本发明还提供了使用本文所述的气相掺杂技术制造的包括例如nFET和/或pFET的CMOS结构。

公开(公告)号：US20070218597A1

公开(公告)日：2007-09-20

申请号：US11384718

申请日：2006-03-15

申请人： Stephen Bedell ,  Joel DeSouza ,  Devendra Sadana ,  Klaus Schwarz ,  Alexander Reznicek

发明人： Stephen Bedell ,  Joel DeSouza ,  Devendra Sadana ,  Klaus Schwarz ,  Alexander Reznicek

IPC分类号： H01L21/8232 ,  H01L21/335

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/78 ,  H01L29/7843

摘要： A structure and method for controlling the behavior of dislocations in strained semiconductor layers is described incorporating a graded alloy region to provide a strain gradient to change the slope or curvature of a dislocation propagating upwards or gliding in the semiconductor layer in the proximity of the source and drain of a MOSFET. The upper surface of the strained semiconductor layer may be roughened and/or contain a dielectric layer or silicide which may be patterned to trap the upper end of dislocations in selected surface areas. The invention solves the problem of dislocation segments passing through both the source and drain of a MOSFET creating leakage currents or shorts therebetween.

摘要翻译： 描述了用于控制应变半导体层中的位错行为的结构和方法，其包括渐变合金区域以提供应变梯度以改变在源附近向上传播或在滑动区域中传播的位错的斜率或曲率， MOSFET的漏极。 应变半导体层的上表面可以被粗糙化和/或包含可以被图案化的介电层或硅化物，以捕获选定表面区域中位错的上端。 本发明解决了通过MOSFET的源极和漏极的位错段产生在其间产生漏电流或短路的问题。

公开(公告)号：US20060249790A1

公开(公告)日：2006-11-09

申请号：US11481525

申请日：2006-07-06

申请人： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

发明人： Tze-chiang Chen ,  Guy Cohen ,  Alexander Reznicek ,  Devendra Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

摘要翻译： 提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。 在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

公开(公告)号：US20050236687A1

公开(公告)日：2005-10-27

申请号：US10830347

申请日：2004-04-22

申请人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

发明人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20070015346A1

公开(公告)日：2007-01-18

申请号：US11522905

申请日：2006-09-19

申请人： Guy Cohen ,  Alexander Reznicek ,  Katherine Saenger ,  Min Yang

发明人： Guy Cohen ,  Alexander Reznicek ,  Katherine Saenger ,  Min Yang

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

摘要翻译： 本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。 根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。 根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。 还公开了用于制造本发明的不同实施例的方法和过程。

公开(公告)号：US20050277260A1

公开(公告)日：2005-12-15

申请号：US10865920

申请日：2004-06-14

申请人： Guy Cohen ,  Alexander Reznicek ,  Katherine Saenger ,  Min Yang

发明人： Guy Cohen ,  Alexander Reznicek ,  Katherine Saenger ,  Min Yang

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

摘要翻译： 本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。 根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。 根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。 还公开了用于制造本发明的不同实施例的方法和过程。