公开(公告)号：US06430093B1

公开(公告)日：2002-08-06

申请号：US09864858

申请日：2001-05-24

申请人： Jarrod Eliason ,  William F. Kraus

发明人： Jarrod Eliason ,  William F. Kraus

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/22

摘要： A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

摘要翻译： 一种用于使用NAND-INVERT电路来控制铁电升压电容器的一个电极的铁电存储器的升压电路。 电容器的另一个节点连接到要升压的节点，可以耦合到字线。 NAND电路具有两个输入，一个耦合到字线，另一个用于接收定时信号。 定时输入上升以启动升压操作，并降低以启动升压电压的去除。 只有在低逻辑电平“0”的任何字线都会影响存储器阵列中的选定字线，从而将变频器输出保持为低电平。 第二实施例将第二N沟道晶体管与逆变器的N沟道晶体管串联，以允许选择浮置逆变器输出，如果希望在其第一向上转换期间更快速地驱动字线高电平。

公开(公告)号：US20070090461A1

公开(公告)日：2007-04-26

申请号：US11567873

申请日：2006-12-07

申请人： Jarrod Eliason ,  Glen Fox ,  Richard Bailey

发明人： Jarrod Eliason ,  Glen Fox ,  Richard Bailey

IPC分类号： H01L23/62

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/20 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

摘要： Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

摘要翻译： 提出了铁电存储器单元（3），其中单元电容器（R）被集成到单元电容器（C）中，以在单元（3）不是单元电容器（3）时抑制电池存储节点（SN）处的电荷累积或电荷损耗 在避免存储器单元访问操作的显着中断的同时被访问。 提供方法（100,200）用于制造其中并联电阻（R）集成在电容器铁电材料（20）中或在形成的封装层（46）中的铁电存储器单元（3）和铁电电容器（C） 超过图案化电容器结构（C）。

公开(公告)号：US20060118841A1

公开(公告)日：2006-06-08

申请号：US11004708

申请日：2004-12-03

申请人： Jarrod Eliason ,  Glen Fox ,  Richard Bailey

发明人： Jarrod Eliason ,  Glen Fox ,  Richard Bailey

IPC分类号： H01L29/94

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/20 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

摘要： Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

摘要翻译： 提出了铁电存储器单元（3），其中单元电容器（R）被集成到单元电容器（C）中，以在单元（3）不是单元电容器（3）时抑制电池存储节点（SN）处的电荷累积或电荷损耗 在避免存储器单元访问操作的显着中断的同时被访问。 提供方法（100,200）用于制造其中并联电阻（R）集成在电容器铁电材料（20）中或在形成的封装层（46）中的铁电存储器单元（3）和铁电电容器（C） 超过图案化电容器结构（C）。

公开(公告)号：US20060098471A1

公开(公告)日：2006-05-11

申请号：US10985137

申请日：2004-11-10

申请人： Jarrod Eliason

发明人： Jarrod Eliason

IPC分类号： G11C11/22 ,  G11C7/10

CPC分类号： G11C11/22 ,  G11C7/20

摘要： Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array includes non-volatile ferroelectric memory cells, and the memory cells of the array are substantially the same in construction to the cells of the configuration data rows. This allows at least some of the circuitry utilized to access data from the primary array to be utilized to access the configuration data, which promotes an efficient use of resources among other things. Additionally, the configuration data can be transferred to volatile registers serially at startup to simplify routing and design and thereby conserve space. The volatile registers are operatively associated with configuration data circuitry that makes use of the configuration data at startup or later time(s).

摘要翻译： 配置数据存储在一行或多行非易失性铁电存储器单元中，其中这些行与主存储器阵列的行相邻地形成。 主存储器阵列包括非易失性铁电存储器单元，并且阵列的存储器单元在结构上与配置数据行的单元基本相同。 这允许用于访问来自主阵列的数据的至少一些电路被用于访问配置数据，这促进了其他事物之间的资源的有效利用。 此外，配置数据可以在启动时串行传输到易失性寄存器，以简化路由和设计，从而节省空间。 易失性寄存器与配置数据电路可操作地相关联，配置数据电路在启动时或稍后时间使用配置数据。

公开(公告)号：US06864738B2

公开(公告)日：2005-03-08

申请号：US10337053

申请日：2003-01-06

申请人： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

发明人： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

IPC分类号： H02M3/07 ,  G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2001/0032 ,  Y02B70/16

摘要： This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

摘要翻译： 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 该CMOS升压器的一个关键思想是在每次存储器访问结束时使用NMOS FET（MN1）将升压电容器（C1）充电至VDD，并使用PMOS FET（MP1，MP2）将电压保持在 在待机期间输出VDD。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET的栅极通过小电容（C2）升压到VDD + Vthn以上，以在每次存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C2）通过其栅极连接到字线升压电容器的NMOSFET（MN2）预充电到VDD。 PMOS FET的栅极短路到其源极，以在升压期间将其关断。

公开(公告)号：US06819601B2

公开(公告)日：2004-11-16

申请号：US10454862

申请日：2003-06-05

申请人： Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

发明人： Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

IPC分类号： G11C700

CPC分类号： G11C11/22

摘要： A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

公开(公告)号：US07233194B2

公开(公告)日：2007-06-19

申请号：US10682125

申请日：2003-10-09

申请人： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

发明人： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2001/0032 ,  Y02B70/16

摘要： This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

摘要翻译： 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 CMOS升压器包括在每个存储器存取结束时将升压电容器（C 1）充电至VDD的NMOS FET（MN 1），并且包括PMOS FET（MP 1，MP 2），以将输出端的电压保持在VDD 待机时。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET（MN 1）的栅极通过小电容器（C 2）升压到VDD + Vthn以上，以在每个存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C 2）通过其栅极连接到字线升压电容器的NMOSFET（MN 2）预充电到VDD。 每个PMOS FET（MP 1，MP 2）的栅极短路到其源极，以在boostenig期间关闭。 晶体管（MP 3）有助于将NMOS FET（MN 1）升压到VDD以上。

公开(公告)号：US06909318B2

公开(公告)日：2005-06-21

申请号：US10649405

申请日：2003-08-27

申请人： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

发明人： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

IPC分类号： H02M3/07 ,  G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073 ,  H02M2001/0032 ,  Y02B70/16

摘要： This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

摘要翻译： 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 CMOS升压器包括在每个存储器存取结束时将升压电容器（C 1）充电至VDD的NMOS FET（MN 1），并且包括PMOS FET（MP 1，MP 2），以将输出端的电压保持在VDD 待机时。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET（MN 1）的栅极通过小电容器（C 2）升压到VDD + Vthn以上，以在每个存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C 2）通过其栅极连接到字线升压电容器的NMOSFET（MN 2）预充电到VDD。 每个PMOS FET（MP 1，MP 2）的栅极短路，以在boostenig期间关闭源。 T晶体管（MP 3）有助于将NMOS FET（MN 1）升压到VDD以上。

公开(公告)号：US06275425B1

公开(公告)日：2001-08-14

申请号：US09714879

申请日：2000-11-16

申请人： Jarrod Eliason

发明人： Jarrod Eliason

IPC分类号： G11C712

CPC分类号： G11C5/145 ,  G11C11/22

摘要： A boost circuit for a ferroelectric memory operated in a low voltage supply environment is achieved by floating a local supply voltage and using a single boost via one or more appropriately sized ferroelectric boost capacitors to elevate the local supply level to the desired boosted voltage. When boosting is not required, the local supply voltage is tied to the system external power supply through an appropriately sized PMOS transistor.

摘要翻译： 用于在低电压供电环境中操作的铁电存储器的升压电路通过漂浮局部电源电压并通过一个或多个适当尺寸的铁电升压电容器使用单个升压来实现，以将局部电源电平提升到期望的升压电压。 当不需要升压时，本地电源电压通过适当尺寸的PMOS晶体管与系统外部电源相连。