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公开(公告)号：US08674423B2
公开(公告)日：2014-03-18
申请号：US13302168
申请日：2011-11-22
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译： 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。
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公开(公告)号：US20100155897A1
公开(公告)日：2010-06-24
申请号：US12342609
申请日：2008-12-23
CPC分类号： H01L29/93 , H01L27/0805 , H01L27/0808 , H01L29/66181 , H01L29/945
摘要： A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.
摘要翻译： 提供了与深沟槽电容器结构兼容的深沟槽变容二极管结构及其制造方法。 掩埋板层形成在第二深沟槽上，同时保护第一沟槽不形成任何掩埋的板层。 深沟槽的内部填充有导电材料以形成内部电极。 在第一深沟槽的外部和邻接部分形成至少一个掺杂阱，并构成至少一个外变容二极管电极。 多个掺杂阱可以并联连接以提供具有电容复杂电压依赖性的变容二极管。 掩埋板层和与其连接的另一个掺杂阱构成形成在第二深沟槽上的线性电容器的外部电极。
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13.发明申请DESIGN STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES THAT SHIELD A BOND PAD FROM ELECTRICAL NOISE 失效设计结构包含电子噪声的粘结垫片的半导体器件结构公开(公告)号：US20090106713A1
公开(公告)日：2009-04-23
申请号：US11877155
申请日：2007-10-23
IPC分类号： G06F17/50
CPC分类号： H01L23/5225 , H01L21/823475 , H01L23/3171 , H01L23/552 , H01L24/05 , H01L27/0688 , H01L2224/02166 , H01L2224/04042 , H01L2224/05 , H01L2224/05093 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes active circuitry on a substrate, a bond pad carried by the substrate, and a shielding structure disposed between the substrate and the bond pad. The shielding structure includes a plurality of electrically characterized devices configured to reduce noise transmission from the active circuitry to the bond pad.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括衬底上的有源电路，由衬底承载的接合焊盘以及设置在衬底和焊盘之间的屏蔽结构。 屏蔽结构包括被配置为减少从有源电路到接合焊盘的噪声传输的多个电特征化器件。
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14.发明授权Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors 有权具有VIAS和高密度电容器结构的结构，设计结构和方法公开(公告)号：US08125013B2
公开(公告)日：2012-02-28
申请号：US12191385
申请日：2008-08-14
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/66181 , H01L29/945
摘要： A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.
摘要翻译： 半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。
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公开(公告)号：US08008748B2
公开(公告)日：2011-08-30
申请号：US12342609
申请日：2008-12-23
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L27/0805 , H01L27/0808 , H01L29/66181 , H01L29/945
摘要： A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench.
摘要翻译： 提供了与深沟槽电容器结构兼容的深沟槽变容二极管结构及其制造方法。 掩埋板层形成在第二深沟槽上，同时保护第一沟槽不形成任何掩埋的板层。 深沟槽的内部填充有导电材料以形成内部电极。 在第一深沟槽的外部和邻接部分形成至少一个掺杂阱，并构成至少一个外变容二极管电极。 多个掺杂阱可以并联连接以提供具有电容复杂电压依赖性的变容二极管。 掩埋板层和与其连接的另一个掺杂阱构成形成在第二深沟槽上的线性电容器的外部电极。
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16.发明申请SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR SHIELDING A BOND PAD FROM ELECTRICAL NOISE 审中-公开半导体器件结构和电子屏蔽屏蔽的方法公开(公告)号：US20090020856A1
公开(公告)日：2009-01-22
申请号：US11778902
申请日：2007-07-17
CPC分类号： H01L23/5225 , H01L23/552 , H01L23/642 , H01L24/05 , H01L27/0203 , H01L2224/02166 , H01L2224/05093 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： Semiconductor device structures and methods for shielding a bond pad from electrical noise generated by active circuitry of an integrated circuit carried on a substrate. The structure includes electrically characterized devices placed in a pre-determined arrangement under the bond pad. The pre-determined arrangement of the electrically characterized devices provides for a consistent high frequency environment under the bond pad, which simplifies modeling of the bond pad by a circuit designer.
摘要翻译： 用于屏蔽接合焊盘的电子器件结构和方法，其由承载在衬底上的集成电路的有源电路产生的电噪声。 该结构包括以特定的布置放置在接合焊盘下方的电特征化器件。 电气特征化器件的预定布置提供了在焊盘下方的一致的高频环境，这简化了电路设计者对接合焊盘的建模。
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公开(公告)号：US08169007B2
公开(公告)日：2012-05-01
申请号：US13037485
申请日：2011-03-01
申请人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
发明人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
CPC分类号： H01L29/1058 , H01L29/0653 , H01L29/0692 , H01L29/0843 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/808
摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。
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18.发明授权Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise 失效结合半导体器件结构的设计结构，可以将接合焊盘屏蔽电气噪声公开(公告)号：US07739636B2
公开(公告)日：2010-06-15
申请号：US11877155
申请日：2007-10-23
CPC分类号： H01L23/5225 , H01L21/823475 , H01L23/3171 , H01L23/552 , H01L24/05 , H01L27/0688 , H01L2224/02166 , H01L2224/04042 , H01L2224/05 , H01L2224/05093 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes active circuitry on a substrate, a bond pad carried by the substrate, and a shielding structure disposed between the substrate and the bond pad. The shielding structure includes a plurality of electrically characterized devices configured to reduce noise transmission from the active circuitry to the bond pad.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括衬底上的有源电路，由衬底承载的接合焊盘以及设置在衬底和焊盘之间的屏蔽结构。 屏蔽结构包括被配置为减少从有源电路到接合焊盘的噪声传输的多个电特征化器件。
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19.发明授权Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors 有权具有VIAS和高密度电容器结构的结构，设计结构和方法公开(公告)号：US08101494B2
公开(公告)日：2012-01-24
申请号：US12191379
申请日：2008-08-14
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译： 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。
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公开(公告)号：US20110147808A1
公开(公告)日：2011-06-23
申请号：US13037485
申请日：2011-03-01
申请人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
发明人： Frederick G. Anderson , David S. Collins , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
IPC分类号： H01L27/098
CPC分类号： H01L29/1058 , H01L29/0653 , H01L29/0692 , H01L29/0843 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/808
摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.
摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。
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