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公开(公告)号：US20100005218A1
公开(公告)日：2010-01-07
申请号：US12165816
申请日：2008-07-01
IPC分类号： G06F12/06
CPC分类号： G06F13/4234
摘要： A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.
摘要翻译： 提供了一种用于提供增强级联互连存储器系统的系统，存储器集线器设备，方法和设计结构。 该系统包括存储器控制器，存储器通道，耦合到存储器通道的存储器集线器设备，以经由另一个存储器集线器设备的直接连接和级联互连中的一个与存储器控制器进行通信，以及与存储控制器通信的多个存储器设备 存储器控制器经由一个或多个级联互连的存储器集线器设备。 存储器通道包括耦合到存储器控制器并且可操作用于传输可配置数据帧的单向下游链路段。 存储器通道还包括耦合到存储器控制器并且可操作用于传送数据帧的单向上游链路段。
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公开(公告)号：US07636813B2
公开(公告)日：2009-12-22
申请号：US11419586
申请日：2006-05-22
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
IPC分类号： G06F13/18 , G06F13/374
CPC分类号： G06F13/1673
摘要： Systems and methods for providing remote pre-fetch buffers. The systems include a computer memory system with a memory controller, one or more memory busses connected to the memory controller, and at least one memory subsystem in communication with the memory controller via the memory busses. The memory controller generates, receives and responds to memory access requests including unsolicited data transfers. The memory subsystem includes one or more memory devices and logic to initiate an unsolicited data transfer to the memory controller based on analysis performed at the memory subsystem of prior memory access requests received by the memory subsystem.
摘要翻译： 用于提供远程预取缓冲区的系统和方法。 这些系统包括具有存储器控制器的计算机存储器系统，连接到存储器控制器的一个或多个存储器总线以及经由存储器总线与存储器控制器通信的至少一个存储器子系统。 存储器控制器生成，接收并响应包括主动请求的数据传输的存储器访问请求。 存储器子系统包括一个或多个存储器设备和逻辑，用于基于在存储器子系统处对由存储器子系统接收的先前存储器访问请求执行的分析来发起向存储器控制器的非请求数据传输。
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公开(公告)号：US20080005496A1
公开(公告)日：2008-01-03
申请号：US11383989
申请日：2006-05-18
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。
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14.发明授权公开(公告)号：US08869153B2
公开(公告)日：2014-10-21
申请号：US12130612
申请日：2008-05-30
CPC分类号： G06F9/505 , G06F9/3851 , G06F2209/5018 , G06F2209/5019 , G06F2209/508
摘要： A method and system for providing quality of service guarantees for simultaneous multithreaded processors are disclosed. Hardware and operating system communicate with one another providing information relating to thread attributes for threads executing on processing elements. The operating system controls scheduling of the threads based at least partly on the information communicated and provides quality of service guarantees.
摘要翻译： 公开了一种用于提供同时多线程处理器的服务质量保证的方法和系统。 硬件和操作系统彼此通信，提供与处理元件上执行的线程的线程属性相关的信息。 操作系统至少部分地基于传达的信息来控制线程的调度，并提供服务质量保证。
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15.发明授权Providing frame start indication in a memory system having indeterminate read data latency 有权在具有不确定的读数据延迟的存储器系统中提供帧起始指示公开(公告)号：US08327105B2
公开(公告)日：2012-12-04
申请号：US13397819
申请日：2012-02-16
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译： 具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。 存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。 数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。 一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。 每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。
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公开(公告)号：US20120066473A1
公开(公告)日：2012-03-15
申请号：US12882551
申请日：2010-09-15
CPC分类号： G06F12/06 , G06F12/10 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.
摘要翻译： 介绍了一种用于存储器管理的计算系统和方法。 存储器或I / O控制器接收写入请求，其中写入的数据2与地址相关联。 提示信息可以与地址相关联，并且可以涉及诸如历史，O / S方向，数据优先级，作业优先级，作业重要性，作业类别，存储器类型，I / O发送者ID，延迟，功率，写入 成本或读取成本组件。 存储器控制器可以询问提示信息以确定存储关联数据的位置（例如，什么存储器类型或类别）。 因此，数据被有效地存储在系统内。 提示信息还可以用于跟踪写入后信息，并且可以被询问以确定是否应该发生数据迁移，并且应该向哪个新的存储器类型或类别移动数据。
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公开(公告)号：US08051276B2
公开(公告)日：2011-11-01
申请号：US11482270
申请日：2006-07-07
IPC分类号： G06F7/38
CPC分类号： G06F9/5033 , G06F1/206 , G06F9/5094 , G06F2209/5013 , G06F2209/5018 , G06F2209/508 , Y02D10/22
摘要： A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.
摘要翻译： 提供了一种用于最佳散热的线程调度的方法和系统。 温度传感器测量处理器芯片各个部分的温度。 检测到的温度被报告给操作系统等用于调度线程。 在一个方面，观察到的温度值记录在寄存器上。 操作系统等读取寄存器并根据温度值调度线程。
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公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US20100250853A1
公开(公告)日：2010-09-30
申请号：US11482222
申请日：2006-07-07
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/6028 , G06F2212/651 , G06F2212/654
摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
摘要翻译： 提供了一种在计算机系统中预取的方法和系统。 该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。 在预取期间解决翻译错误的处理和解决。 该方法还包括将分辨的翻译存储在相应的缓存转换表中。 用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。 如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。 如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。
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公开(公告)号：US07523290B2
公开(公告)日：2009-04-21
申请号：US10672376
申请日：2003-09-26
申请人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith , Robert B. Tremaine , Michael Wazlowski
发明人： Peter A. Franaszek , Charles O. Schulz , T. Basil Smith , Robert B. Tremaine , Michael Wazlowski
IPC分类号： G06F12/00
CPC分类号： G06F12/1009
摘要： A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.
摘要翻译： 一种计算系统和方法，所述计算系统和方法采用处理器设备来生成与实际存储器系统的存储器位置相关联的用于读取和写入数据的实际地址，所述系统包括：所述实际存储器系统中的用于存储数据的多个存储块， 用于存储包括一个或多个实际存储器块的数据页面的存储器存储器，每个实际存储器块被划分成一个或多个扇区，每个扇区包括物理存储器的连续字节; 物理存储器存储器中的转换表结构具有用于将实际地址与物理存储器的扇区相关联的条目，每个转换表条目包括用于指向其相关联的实际存储器块中的对应扇区的一个或多个指针， 用于由处理器发起的用于存储器读和写操作的一个或多个分配扇区中的数据; 以及用于直接操纵翻译表结构中的条目以执行页面操作而不实际访问物理存储器数据内容的控制装置。 在该系统中，操作所涉及的页面的实际数据从不被处理器访问，因此在存储器高速缓存层次结构中从不需要这样的数据，从而消除通常与这些块操作相关联的高速缓存损坏。 此外，翻译表的操作将涉及读取和写入几个字节以执行操作，而不是在被操纵的页面中读取和写入数百或数千字节。
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