公开(公告)号：US07301821B1

公开(公告)日：2007-11-27

申请号：US11251074

申请日：2005-10-13

申请人： Jonathan Greene ,  Robert M. Salter, III

发明人： Jonathan Greene ,  Robert M. Salter, III

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/3431 ,  G11C29/50 ,  H03K19/17776 ,  H03K19/1778

摘要： A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.

摘要翻译： 一种用于将数据存储在非易失性存储单元阵列的存储单元中的节点的方法，包括将非易失性存储单元阵列的非易失性设备设置为期望状态的步骤，将上拉设备和非易失性设备偏置 所述非易失性存储单元阵列的第一组行到关闭状态，将数据加载到所述非易失性存储单元阵列的列线上并且偏置所述非易失性存储单元阵列的存储单元中的第二组行中的非易失性设备， 非易失性存储单元阵列，用于存储来自非易失性存储单元阵列的存储单元中节点上列列的数据。

公开(公告)号：US6137728A

公开(公告)日：2000-10-24

申请号：US205678

申请日：1998-12-04

申请人： Jack Zezhong Peng ,  Volker Hecht ,  Robert M. Salter, III ,  Kyung Joon Han ,  Robert U. Broze

发明人： Jack Zezhong Peng ,  Volker Hecht ,  Robert M. Salter, III ,  Kyung Joon Han ,  Robert U. Broze

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792 ,  H03K19/177

CPC分类号： H01L27/11803 ,  G11C16/0441 ,  H01L27/115

摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor. The source/drains of the sense field effect transistor are formed from buried doped layers (e.g. N+ in a P-doped substrate) which are formed prior to formation of the polysilicon floating gate and control gate. Lateral diffusion of dopant from the buried source/drains into the channel beneath the floating gate facilitates electron tunneling during erase and program operations, and the graded junctions of the buried source/drains lower band-to-band tunneling leakage.

摘要翻译： 公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。 每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。 通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。 感测场效应晶体管的源极/漏极由在形成多晶硅浮置栅极和控制栅极之前形成的掩埋掺杂层（例如P掺杂衬底中的N +）形成。 掺杂剂从掩埋源/漏极到浮置栅极下方的沟道的横向扩散有助于在擦除和编程操作期间的电子隧穿，并且埋入源/分级结的接合点降低带对带隧穿泄漏。

公开(公告)号：US5566344A

公开(公告)日：1996-10-15

申请号：US445006

申请日：1995-05-19

申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Richard E. Crippen ,  Robert M. Salter, III

发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Richard E. Crippen ,  Robert M. Salter, III

IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die. The address and program data are then parallel output from separate registers on the memory die along with a program pulse to program the memory core.

摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 处理器可以在内部或外部进行编程。 在系统内编程模式下，处理器程序计数器用于从处理器管芯上的板载ROM指令存储器中获取运行指令。 处理器内核在其输出数据总线上输出要编程数据的地址。 然后，处理器核心从外部设备接收要被编程到所选择的地址中的数据，并将其串行地输出到数据总线上并从其输出到存储器管芯。 然后，地址和程序数据与存储器管芯上的单独寄存器一起并行输出，并且与编程脉冲一起编程存储器内核。

公开(公告)号：US08803548B2

公开(公告)日：2014-08-12

申请号：US13450765

申请日：2012-04-19

申请人： Robert M. Salter, III

发明人： Robert M. Salter, III

IPC分类号： H03K19/177 ,  G06F21/76

CPC分类号： H03K19/17768 ,  G06F21/85

摘要： A tamper-resistant bus architecture for secure lock bit transfer in an integrated circuit includes a nonvolatile memory having an n-bit storage region for storing encoded lock bits, A plurality of read access circuits are coupled to the nonvolatile memory. An n-bit tamper-resistant bus is coupled to the read access circuits. A decoder is coupled to the tamper-resistant bus. A k-bit decoded lock signal bus is coupled to the decoder. A controller is coupled to the k-bit decoded lock signal bus.

摘要翻译： 用于在集成电路中进行安全锁定位传输的防篡改总线架构包括具有用于存储编码锁定位的n位存储区域的非易失性存储器。多个读取访问电路耦合到非易失性存储器。 n位抗篡改总线耦合到读访问电路。 解码器耦合到防篡改总线。 k位解码锁定信号总线耦合到解码器。 控制器耦合到k位解码锁定信号总线。

公开(公告)号：US6072720A

公开(公告)日：2000-06-06

申请号：US205876

申请日：1998-12-04

申请人： Jack Zezhong Peng ,  Robert M. Salter, III ,  Volker Hecht ,  Kyung Joon Han ,  Robert U. Broze ,  Victor Levchenko

发明人： Jack Zezhong Peng ,  Robert M. Salter, III ,  Volker Hecht ,  Kyung Joon Han ,  Robert U. Broze ,  Victor Levchenko

IPC分类号： G11C16/04 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/088 ,  H01L27/115 ,  H01L27/118 ,  H01L29/788 ,  H01L29/792 ,  H03K19/177

CPC分类号： H01L27/11521 ,  G11C16/0441 ,  H01L27/11524

摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.

摘要翻译： 公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。 每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是共同的，并且控制栅极是共同的。 单元的编程通过与开关晶体管和感测晶体管并置的埋入位线来实现，开关晶体管和浮动栅极和控制栅极在其上。 感测晶体管可以与开关晶体管的制造同时制造，由此两个晶体管的掺杂剂浓度相同。

公开(公告)号：US5838040A

公开(公告)日：1998-11-17

申请号：US829374

申请日：1997-03-31

申请人： Robert M. Salter, III ,  Kyung Joon Han ,  Jack Zezhong Peng ,  Victor Levchenko ,  Robert V. Broze

发明人： Robert M. Salter, III ,  Kyung Joon Han ,  Jack Zezhong Peng ,  Victor Levchenko ,  Robert V. Broze

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/82 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03K19/173

CPC分类号： G11C16/0441 ,  H01L27/115

摘要： Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.

摘要翻译： 公开了一种使用FN隧道进行编程和擦除的FPGA单元和阵列结构。 每个单元包括开关浮置栅极场效应晶体管和感测浮置栅极场效应晶体管，其中浮动栅极是公共的，并且控制栅极是共同的。 通过对公共控制栅极线和感测晶体管的源极/漏极的电压偏置来实现单元的编程。

公开(公告)号：US5623686A

公开(公告)日：1997-04-22

申请号：US446079

申请日：1995-05-19

申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.

摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 非易失性存储器管芯上的输入数据寄存器和相关的多路复用器允许根据操作模式将来自不同源的数据加载到输入数据寄存器中。 此外，输入数据寄存器的输出耦合到多个位置，使得数据的目的地也可以响应于操作模式而被切换。 特别地，输入数据寄存器的输出耦合到输出端口，程序数据寄存器（程序数据可以通过其加载到程序存储器中）和控制寄存器，用于设置用于执行特定完整性测试的各种控制位， 在制造之后执行。 因此，输入数据寄存器用于从外部源编程存储器，从外部设备设置控制位，并将数据从处理器发送到R端口并传输到外部设备。

公开(公告)号：US5581779A

公开(公告)日：1996-12-03

申请号：US445007

申请日：1995-05-19

申请人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

发明人： Christopher M. Hall ,  Gary D. Phillips ,  William E. Miller ,  David W. Weinrich ,  Robert M. Salter, III ,  Richard E. Crippen

IPC分类号： G06F15/78 ,  G11C16/10 ,  G06F15/76

CPC分类号： G11C16/102 ,  G06F15/7814 ,  Y02B60/1207 ,  Y02B60/1225

摘要： An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

摘要翻译： 一种用于串行多芯片封装数字控制器的架构，包括面向控制器的处理器管芯和单独的非易失性存储器管芯。 该架构通过利用有效的多路复用来提供封装上的低引脚数，骰子之间和之间的最小电连接以及最小数量的寄存器，以允许许多寄存器和信号线响应于该模式而提供多个功能 的操作和其他控制信号。 处理器包括分别包括处理器管芯和存储管芯上的第一和第二存储器接口控制寄存器的系统内编程模式，用于从处理器核心接收控制位以控制管芯上的多路复用器。 第一存储器接口控制寄存器的各个位输出线耦合到多路复用器的控制输入端。

公开(公告)号：US5359555A

公开(公告)日：1994-10-25

申请号：US847114

申请日：1992-03-06

申请人： Robert M. Salter, III

发明人： Robert M. Salter, III

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  G11C11/34

CPC分类号： G11C16/0491 ,  G11C16/10

摘要： A CMOS memory is disclosed which employs a column selector circuit that prevents write disturb in shared column EPROMs. When a selected memory transistor is programmed, disturb is prevented by selecting all columns on the source side of the selected memory transistor to be tied to the source programming voltage, and selecting all columns on the drain side of the selected memory transistor to be tied to the drain programming voltage. By reducing voltage differentials across non-selected memory transistors, write disturb is prevented. This may be implemented by employing shorting devices between all adjacent columns. When a memory transistor is selected, all the shorting devices except the one between the source and drain columns of the selected memory cell are enabled. This may be further improved to minimize the number of required select lines by employing a shorting device comprising transistors controlled by the normal select lines.

摘要翻译： 公开了一种采用列选择器电路的CMOS存储器，该电路防止共享列EPROM中的写入干扰。 当选择的存储晶体管被编程时，通过选择所选择的存储晶体管的源极上的所有列被连接到源编程电压来防止干扰，并且将所选存储晶体管的漏极侧上的所有列选择为被连接到 漏极编程电压。 通过降低非选择存储晶体管的电压差，可以防止写干扰。 这可以通过在所有相邻列之间采用短路装置来实现。 当选择存储晶体管时，除了所选存储单元的源极和漏极列之外的所有短路装置都被使能。 这可以进一步改进，以通过采用包括由普通选择线控制的晶体管的短路装置来最小化所需选择线的数量。