公开(公告)号：US07804150B2

公开(公告)日：2010-09-28

申请号：US11479149

申请日：2006-06-29

申请人： Chang-ki Jeon ,  Gary Dolny

发明人： Chang-ki Jeon ,  Gary Dolny

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/7825 ,  H01L29/0634 ,  H01L29/0696

摘要： A field effect transistor includes a trench gate extending into a semiconductor region. The trench gate has a front wall facing a drain region and a side wall perpendicular to the front wall. A channel region extends along the side wall of the trench gate, and a drift region extends at least between the drain region and the trench gate. The drift region includes a stack of alternating conductivity type silicon layers.

摘要翻译： 场效应晶体管包括延伸到半导体区域中的沟槽栅极。 沟槽门具有面向漏区的前壁和垂直于前壁的侧壁。 沟道区域沿着沟槽栅极的侧壁延伸，并且漂移区域至少在漏极区域和沟槽栅极之间延伸。 漂移区域包括一叠交替导电型硅层。

公开(公告)号：US07605040B2

公开(公告)日：2009-10-20

申请号：US11828128

申请日：2007-07-25

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66674 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

摘要： A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.

摘要翻译： 形成金属氧化物半导体（MOS）晶体管的方法包括以下步骤。 提供第一导电性的衬底。 在衬底上形成第二导电类型的第一掩埋层。 第一导电类型的第二掩埋层形成在第一掩埋层中。 在衬底上形成第二导电类型的外延层。 在外延层中形成第二导电类型的漂移区。 在漂移区上形成栅极层。 第一导电类型的体区形成在漂移区域中，使得栅极与身体区域的表面部分重叠。 在身体区域中形成第二导电性的源极区域。 在漂移区域中形成第二导电类型的漏极区域。 漏极区域与身体区域横向间隔开。 第一和第二掩埋层从身体区域下方横向延伸到漏极区域下方。 体区域的表面部分在源极区域和漂移区域之间延伸以形成晶体管的沟道区域。

公开(公告)号：US20070158681A1

公开(公告)日：2007-07-12

申请号：US11329268

申请日：2006-01-09

申请人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

发明人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

IPC分类号： H01L29/74

CPC分类号： H01L29/808 ,  H01L27/088

摘要： In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.

摘要翻译： 在一个实施例中，提供了功率集成电路器件。 功率集成电路装置包括具有高压晶体管和低压晶体管的高侧电源开关。 高压晶体管具有栅极，源极和漏极，并且能够承受施加到其漏极的高电压。 低压晶体管具有栅极，源极和漏极，其中低压晶体管的漏极连接到高压晶体管的源极，并且低压晶体管的源极连接到高电压的栅极 晶体管，并且其中控制信号从功率集成电路器件施加到低电压晶体管的栅极。 当向低电压晶体管的源极施加预定电压时，高侧电源开关接通，将高于预定电压的电压施加到高压晶体管的漏极，并且控制信号的电压电平 通过低压晶体管的阈值电压变得高于预定电压。

公开(公告)号：US06600206B2

公开(公告)日：2003-07-29

申请号：US10123007

申请日：2002-04-15

申请人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Jong-jib Kim

发明人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Jong-jib Kim

IPC分类号： H01L2900

CPC分类号： H01L29/7816 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095

摘要： A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

摘要翻译： 提供高压半导体器件。 高电压半导体器件包括丝束电压区域，高电压区域和高击穿电压隔离区域。 高电压区域被低电压区域包围，并且在其一侧具有角部。 高击穿电压隔离区域具有用于将低电压区域和高电压区域彼此电隔离的隔离区域和用于将信号从低电压区域传输到高电压区域的横向双扩散金属氧化物半导体（DMOS）晶体管 。 特别地，横向DMOS晶体管的漏极区域设置在高电压区域的角部之间，并且横向DMOS晶体管的高压区域和漏极区域的拐角部分的相对边缘是弯曲的。

公开(公告)号：US06486512B2

公开(公告)日：2002-11-26

申请号：US09790815

申请日：2001-02-23

申请人： Chang-ki Jeon ,  Jong-jib Kim ,  Young-suk Choi ,  Chang-seong Choi ,  Min-whan Kim

发明人： Chang-ki Jeon ,  Jong-jib Kim ,  Young-suk Choi ,  Chang-seong Choi ,  Min-whan Kim

IPC分类号： H01L2976

CPC分类号： H01L29/0692 ,  H01L29/0696 ,  H01L29/7835

摘要： A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed. As a result, a power semiconductor device having a small radius of curvature of the source structure and a high breakdown voltage can be provided.

摘要翻译： 提供了功率半导体器件及其制造方法。 功率半导体器件包括源结构，其具有在其中心具有尖端形状的端部的突出部分并且形成为围绕突出部分的左右上部的预定区域。 在由源结构包围的预定区域中形成两个漏极结构。 在漏极结构周围形成扩展的漏极结构，并且延伸的漏极结构用作具有源结构的突出部分的侧面之间的场效应沟道的沟道。 因此，由于在源极结构的突出部分的尖端上没有漏极结构，尽管突出部分的尖端的曲率半径小，但是由于半径小的部件，器件的击穿电压降低 可以抑制突出部分的尖端的弯曲。 结果，可以提供具有较小的源结构曲率半径和高击穿电压的功率半导体器件。

公开(公告)号：US08097510B2

公开(公告)日：2012-01-17

申请号：US12890947

申请日：2010-09-27

申请人： Chang-ki Jeon ,  Gary Dolny

发明人： Chang-ki Jeon ,  Gary Dolny

IPC分类号： H01L21/336

CPC分类号： H01L29/7825 ,  H01L29/0634 ,  H01L29/0696

摘要： A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type silicon layers; forming a trench gate extending into the stack of alternating conductivity type silicon layers, the trench gate having a non-active sidewall and an active sidewall being perpendicular to one another; and forming a body region of a second conductivity type adjacent to the active sidewall of the trench gate, wherein the trench gate and the drain region are formed such that the non-active sidewall of the trench gate faces the drain region.

摘要翻译： 形成场效应晶体管（FET）的方法包括：形成包括交替导电型硅层叠层的漂移区; 形成延伸到交替导电型硅层堆叠中的第一导电类型的漏区; 形成延伸到交替导电型硅层的堆叠中的沟槽栅极，所述沟槽栅极具有非活性侧壁和主动侧壁彼此垂直; 以及形成与所述沟槽栅极的有源侧壁相邻的第二导电类型的主体区域，其中所述沟槽栅极和漏极区域形成为使得所述沟槽栅极的非有源侧壁面向所述漏极区域。

公开(公告)号：US07265416B2

公开(公告)日：2007-09-04

申请号：US10366545

申请日：2003-02-12

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/66674 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

摘要： In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift region. A source region of the second conductivity is in the body region. A gate extends over a surface portion of the body region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor. A drain region of the second conductivity type is in the drift region. The drain region is laterally spaced from the body region. A first buried layer of the second conductivity type is between the substrate and drift region. The first buried layer laterally extends from under the body region to under the drain region. A second buried layer of the first conductivity type is between the first buried layer and the drift region. The second buried layer laterally extends from under the body region to under the drain region.

摘要翻译： 根据本发明，金属氧化物半导体（MOS）晶体管具有第一导电类型的衬底。 第二导电类型的漂移区域在衬底上延伸。 第一导电类型的体区在漂移区中。 第二导电性的源极区域在体区域中。 门延伸到身体区域的表面部分上。 体区域的表面部分在源极区域和漂移区域之间延伸以形成晶体管的沟道区域。 第二导电类型的漏区在漂移区中。 漏极区域与身体区域横向间隔开。 第二导电类型的第一掩埋层位于衬底和漂移区之间。 第一掩埋层从身体区域下方横向延伸到漏极区域下方。 第一导电类型的第二掩埋层位于第一掩埋层和漂移区之间。 第二掩埋层从身体区域下方横向延伸到漏极区域下方。

公开(公告)号：US20060237815A1

公开(公告)日：2006-10-26

申请号：US11378210

申请日：2006-03-16

申请人： Sung-lyong Kim ,  Chang-ki Jeon

发明人： Sung-lyong Kim ,  Chang-ki Jeon

IPC分类号： H01L29/00

CPC分类号： H01L29/8611 ,  H01L27/0629 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/868 ,  H01L2924/0002 ,  H03K17/6877 ,  H03K2217/0036 ,  H01L2924/00

摘要： Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented.

摘要翻译： 提供一种包括耐高压二极管的高压集成电路装置。 该器件包括具有多个相对于接地电压工作的多个半导体器件的低电压电路区域，具有多个半导体器件的高电压电路区域，其相对于从地面变化的电压工作 电压到高电压，接合端接和将低压电路区域与高压电路区域电隔离的第一隔离区域，形成在低压电路区域和高压电路之间的高耐压二极管 以及围绕所述耐高压二极管的第二隔离区域，并且将所述耐高压二极管与所述低压电路区域和所述高压电路区域电隔离。 因此，可以防止高耐压二极管的漏电流。

公开(公告)号：US20050253218A1

公开(公告)日：2005-11-17

申请号：US11114693

申请日：2005-04-26

申请人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

发明人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Tae-hun Kwon

IPC分类号： H01L21/335 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7823

摘要： There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.

摘要翻译： 提供了高压栅极驱动器集成电路。 高压栅极驱动器集成电路包括：高电压区域; 围绕高电压区域的接合端接区域; 围绕所述连接端接区域的低电压区域; 设置在所述高电压区域和所述低电压区域之间的电平移位晶体管，所述电平移位晶体管的至少一些部分与所述连接终止区域重叠; 和/或设置在高电压区域和低电压区域之间的高压结电容器，高压结电容器的至少一些部分与接合端接区域重叠。

公开(公告)号：US06218725B1

公开(公告)日：2001-04-17

申请号：US09371041

申请日：1999-08-10

申请人： Chang-ki Jeon

发明人： Chang-ki Jeon

IPC分类号： H01L27082

CPC分类号： H01L29/66272 ,  H01L21/28512 ,  H01L21/763 ,  H01L29/0821 ,  H01L29/7322

摘要： A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate. An intrinsic base region is formed into the well region and an emitter region into the intrinsic base region using the device isolation layer as a mask. The bipolar transistor and method of fabrication can reduce the chip size, the production costs, and the resistance of the collector by forming the isolation trench, wherein the isolation trench is used to form the buried layer and functions as a sink layer (collector layer). The process provides self-alignment of the extrinsic base region, the intrinsic base region, and the emitter region to reduce process scattering.

摘要翻译： 提供了双极晶体管及其制造方法，其适于减小芯片尺寸和生产成本。 为了制造晶体管，在第一导电型半导体衬底中形成第二导电类型阱区，并且在阱区的两侧形成隔离沟槽。 在形成在隔离沟槽的底部的半导体衬底中形成高密度第二导电型掩埋层。 掩埋层形成在两个相邻隔离沟槽的相应底部周围的两个区域中。 两个区域彼此电连接并且与阱区域直接接触。 使用硝化层图案作为掩模，在半导体衬底上顺序地形成非本征基区和器件隔离区，其中在半导体衬底的表面上形成硝化层图案。 使用器件隔离层作为掩模，将本征基极区域形成为阱区域和发射极区域到本征基极区域。 双极晶体管和制造方法可以通过形成隔离沟槽来减小芯片尺寸，生产成本和集电极的电阻，其中隔离沟槽用于形成埋层并用作沉积层（集电极层） 。 该方法提供外部碱性区域，本征碱基区域和发射极区域的自对准，以减少工艺散射。