公开(公告)号：US08399923B2

公开(公告)日：2013-03-19

申请号：US12495948

申请日：2009-07-01

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Min-suk Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Min-suk Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/7816

摘要： Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.

摘要翻译： 提供一种在半导体衬底的整个表面上形成场成形层的高电压半导体器件及其制造方法。 具体地，高电压半导体器件包括第一导电型半导体衬底。 在半导体衬底的表面上设置第二导电型半导体层，在半导体层中形成第一导电型体区。 在体区域中形成第二导电型源极区域。 在半导体层中形成漏区，与体区分离。 在与半导体层相对的半导体层的整个表面上形成场成形层。

公开(公告)号：US07777524B2

公开(公告)日：2010-08-17

申请号：US12402528

申请日：2009-03-12

申请人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

发明人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

IPC分类号： H03K19/0175

CPC分类号： H01L27/088 ,  H01L21/823481

摘要： Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

摘要翻译： 提供一种包括将低电压单元与高电压单元电隔离的接合端子的高压半导体器件及其制造方法。 高电压半导体器件包括高电压单元，围绕高电压单元的低电压单元，以及形成在高电压单元和低电压单元之间并且围绕高电压单元的连接端子，以将高压单元与 低压单位。 所述连接终端包括至少一个电平移位器，其将来自所述低电压单元的信号电平移位并将其提供给所述高压单元;围绕所述高压单元的第一器件隔离区，以将所述高压单元与所述电平移位器电隔离; 以及电连接相邻电平移位器的电阻层。

公开(公告)号：US20100001343A1

公开(公告)日：2010-01-07

申请号：US12495948

申请日：2009-07-01

申请人： Yong-cheol CHOI ,  Chang-ki JEON ,  Min-suk KIM

发明人： Yong-cheol CHOI ,  Chang-ki JEON ,  Min-suk KIM

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/7816

摘要： Provided are a high voltage semiconductor device in which a field shaping layer is formed on the entire surface of a semiconductor substrate and a method of fabricating the same. Specifically, the high voltage semiconductor device includes a first conductivity-type semiconductor substrate. A second conductivity-type semiconductor layer is disposed on a surface of the semiconductor substrate, and a first conductivity-type body region is formed in semiconductor layer. A second conductivity-type source region is formed in the body region. A drain region is formed in the semiconductor layer and is separated from the body region. The field shaping layer is formed on the entire surface of the semiconductor layer facing the semiconductor layer.

摘要翻译： 提供一种在半导体衬底的整个表面上形成场成形层的高电压半导体器件及其制造方法。 具体地，高电压半导体器件包括第一导电型半导体衬底。 在半导体衬底的表面上设置第二导电型半导体层，在半导体层中形成第一导电型体区。 在体区域中形成第二导电型源极区域。 在半导体层中形成漏区，与体区分离。 在与半导体层相对的半导体层的整个表面上形成场成形层。

公开(公告)号：US20070264785A1

公开(公告)日：2007-11-15

申请号：US11828128

申请日：2007-07-25

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

IPC分类号： H01L27/085

CPC分类号： H01L29/66674 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

摘要： A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.

摘要翻译： 形成金属氧化物半导体（MOS）晶体管的方法包括以下步骤。 提供第一导电性的衬底。 在衬底上形成第二导电类型的第一掩埋层。 第一导电类型的第二掩埋层形成在第一掩埋层中。 在衬底上形成第二导电类型的外延层。 在外延层中形成第二导电类型的漂移区。 在漂移区上形成栅极层。 第一导电类型的体区形成在漂移区域中，使得栅极与身体区域的表面部分重叠。 在身体区域中形成第二导电性的源极区域。 在漂移区域中形成第二导电类型的漏极区域。 漏极区域与身体区域横向间隔开。 第一和第二掩埋层从身体区域下方横向延伸到漏极区域下方。 体区域的表面部分在源极区域和漂移区域之间延伸以形成晶体管的沟道区域。

公开(公告)号：US06207484B1

公开(公告)日：2001-03-27

申请号：US09409914

申请日：1999-09-30

申请人： Jong-Hwan Kim ,  Suk-Kyun Lee ,  Yong-Cheol Choi ,  Chul-Joong Kim

发明人： Jong-Hwan Kim ,  Suk-Kyun Lee ,  Yong-Cheol Choi ,  Chul-Joong Kim

IPC分类号： H01L218238

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： A method for fabricating a BiCDMOS device where bipolar, CMOS and DMOS transistors are formed on a single wafer is provided. A semiconductor region of a second conductivity type is formed on a semiconductor substrate of a first conductivity type. Well regions of first and second conductivity types are formed within the semiconductor region. Then, an oxidation passivation layer pattern defining a region where a pad oxide layer and a field oxide layer are to be formed is formed on a surface of the substrate where the well regions have been formed. Impurity ions of the first conductivity type are implanted into the entire surface of a region where the field oxide layer is to be formed, using the oxidation passivation layer pattern as an ion implantation mask. An ion implantation mask pattern defining a field region of the second conductivity type is formed on the substrate where the oxidation passivation layer has been formed. Impurity ions of the second conductivity type are implanted, using the ion implantation mask pattern. Then, the ion implantation mask pattern is removed. The field oxide layer is formed by annealing, using the oxidation passivation layer pattern, and simultaneously field regions of the first and the second conductivity types are formed.

摘要翻译： 提供一种用于制造BiCDMOS器件的方法，其中在单个晶片上形成双极，CMOS和DMOS晶体管。 在第一导电类型的半导体衬底上形成第二导电类型的半导体区域。 第一和第二导电类型的阱区形成在半导体区域内。 然后，在形成有阱区的基板的表面上形成定义要形成焊盘氧化物层和场氧化物层的区域的氧化钝化层图案。 使用氧化钝化层图案作为离子注入掩模将第一导电类型的杂质离子注入到要形成场氧化物层的区域的整个表面。 在形成氧化钝化层的基板上形成限定第二导电类型的场区的离子注入掩模图案。 使用离子注入掩模图案注入第二导电类型的杂质离子。 然后，去除离子注入掩模图案。 通过使用氧化钝化层图案退火形成场氧化物层，同时形成第一和第二导电类型的场区。

公开(公告)号：US09048210B2

公开(公告)日：2015-06-02

申请号：US13550032

申请日：2012-07-16

申请人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

发明人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

IPC分类号： H01L29/36 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/36 ,  H01L29/6634 ,  H01L29/7397

摘要： A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

摘要翻译： 晶体管包括器件部分和集电极层。 器件部分位于半导体衬底的第一侧，并且包括栅极和发射极。 集电极层位于半导体衬底的与第一侧相对的第二侧上。 集电极层是杂质掺杂的外延层，并具有非正态分布的掺杂分布。

公开(公告)号：US07605040B2

公开(公告)日：2009-10-20

申请号：US11828128

申请日：2007-07-25

申请人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

发明人： Yong-cheol Choi ,  Chang-ki Jeon ,  Cheol-joong Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66674 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

摘要： A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.

摘要翻译： 形成金属氧化物半导体（MOS）晶体管的方法包括以下步骤。 提供第一导电性的衬底。 在衬底上形成第二导电类型的第一掩埋层。 第一导电类型的第二掩埋层形成在第一掩埋层中。 在衬底上形成第二导电类型的外延层。 在外延层中形成第二导电类型的漂移区。 在漂移区上形成栅极层。 第一导电类型的体区形成在漂移区域中，使得栅极与身体区域的表面部分重叠。 在身体区域中形成第二导电性的源极区域。 在漂移区域中形成第二导电类型的漏极区域。 漏极区域与身体区域横向间隔开。 第一和第二掩埋层从身体区域下方横向延伸到漏极区域下方。 体区域的表面部分在源极区域和漂移区域之间延伸以形成晶体管的沟道区域。

公开(公告)号：US08072029B2

公开(公告)日：2011-12-06

申请号：US12013354

申请日：2008-01-11

申请人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

发明人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/7835

摘要： A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension.

摘要翻译： 高电压半导体器件包括第一导电类型的源极区域，其具有两侧的细长突起和半导体衬底中的圆形尖端。 第一导电类型的漏极区域与半导体衬底中的源极区域横向间隔开。 栅电极沿着半导体衬底上的源极区域的源极和漏极区域的突出部分延伸。 第二导电类型的顶部浮动区域设置在沿着源极区域的投影的圆形尖端延伸的弓形条形状的源极和漏极区域之间。 顶部浮动区域通过第一导电类型的区域彼此横向间隔开，从而沿横向尺寸形成交替的P-N区域。

公开(公告)号：US20090243696A1

公开(公告)日：2009-10-01

申请号：US12402528

申请日：2009-03-12

申请人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

发明人： Chang-ki Jeon ,  Min-suk Kim ,  Yong-cheol Choi

IPC分类号： H03L5/00 ,  H01L21/76

CPC分类号： H01L27/088 ,  H01L21/823481

摘要： Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters.

摘要翻译： 提供一种包括将低电压单元与高电压单元电隔离的接合端子的高压半导体器件及其制造方法。 高电压半导体器件包括高电压单元，围绕高电压单元的低电压单元，以及形成在高电压单元和低电压单元之间并且围绕高电压单元的连接端子，以将高压单元与 低压单位。 所述连接终端包括至少一个电平移位器，其将来自所述低电压单元的信号电平移位并将其提供给所述高压单元;围绕所述高压单元的第一器件隔离区，以将所述高压单元与所述电平移位器电隔离; 以及电连接相邻电平移位器的电阻层。

公开(公告)号：US20130200427A1

公开(公告)日：2013-08-08

申请号：US13550032

申请日：2012-07-16

申请人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

发明人： Hyung-su Jeong ,  Jai-kwang Shin ,  Nam-young Lee ,  Ji-hoon Lee ,  Min-kwon Cho ,  Yong-cheol Choi ,  Hyuk-soon Choi

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/36 ,  H01L29/6634 ,  H01L29/7397

摘要： A transistor includes a device portion and a collector layer. The device portion is in a first side of a semiconductor substrate, and includes a gate and an emitter. The collector layer is on a second side of the semiconductor substrate, which is opposite to the first side. The collector layer is an impurity-doped epitaxial layer and has a doping profile with a non-normal distribution.

摘要翻译： 晶体管包括器件部分和集电极层。 器件部分位于半导体衬底的第一侧，并且包括栅极和发射极。 集电极层位于半导体衬底的与第一侧相对的第二侧上。 集电极层是杂质掺杂的外延层，并具有非正态分布的掺杂分布。