公开(公告)号：US20060152467A1

公开(公告)日：2006-07-13

申请号：US11327688

申请日：2006-01-06

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： G09G3/36

CPC分类号： H03K19/0005 ,  G11C7/1051 ,  G11C7/1057 ,  H03K17/164

摘要： A data output driver and a semiconductor memory device having the same are disclosed. This data output driver includes: a rising transition slope adjuster including a plurality of first delay units cascade-connected to each other and receiving data and generating delayed data, each of the first delay units having a delay time which varies in response to a first control signal; a falling transition slope adjuster including a plurality of second delay units cascade-connected to each other and receiving inverted data and generating delayed inverted data, each of the second delay units having a delay time which varies in response to a second control signal; a pull-up driver including a plurality of pull-up circuits, the driving capabilities of the pull-up circuits being adjustable in response to a third control signal, each pull-up circuit pulling-up output data in response to each of the data and the delayed data; and a pull-down driver including a plurality of pull-down circuits, the driving capabilities of the pull-down circuits being adjustable in response to a fourth control signal, each pull-down circuit pulling-down output data in response to each of the inverted data and the delayed inverted data, wherein the first control signal varies in response to the third control signal, and wherein the second control signal varies in response to the fourth control signal. Accordingly, the rising and falling transition slopes of the output data can be constant even when the driving capability is varied, so that output data having desired characteristics can be produced.

摘要翻译： 公开了一种数据输出驱动器及其半导体存储器件。 该数据输出驱动器包括：上升过渡斜率调整器，包括彼此级联的多个第一延迟单元，并接收数据并产生延迟数据，每个第一延迟单元具有响应于第一控制而变化的延迟时间 信号; 一个下降的转变斜率调节器，包括彼此级联的多个第二延迟单元，并接收反相数据并产生延迟的反相数据，每个第二延迟单元具有响应于第二控制信号变化的延迟时间; 包括多个上拉电路的上拉驱动器，上拉电路的驱动能力可响应于第三控制信号而被调节，每个上拉电路响应于每个数据提取输出数据 和延迟数据; 以及包括多个下拉电路的下拉驱动器，所述下拉电路的驱动能力响应于第四控制信号而是可调节的，每个下拉电路根据每个下拉电路的每个下拉输出数据 反转数据和延迟反转数据，其中第一控制信号响应于第三控制信号而变化，并且其中第二控制信号响应于第四控制信号而变化。 因此，即使驱动能力变化，输出数据的上升和下降转换斜率也可以是恒定的，从而可以产生具有期望特性的输出数据。

公开(公告)号：US5555931A

公开(公告)日：1996-09-17

申请号：US299503

申请日：1994-08-01

申请人： Dong-Jin Lee ,  Jeom-Yul Yun

发明人： Dong-Jin Lee ,  Jeom-Yul Yun

IPC分类号： F28F1/00 ,  F28F1/32 ,  F28F9/26

CPC分类号： F28F9/26 ,  F28F1/32

摘要： A small-sized heat exchanger for separable air conditioner not only saving the electric power but also reducing the cost. The heat exchanger has tube banks provided on a predetermined upper section of the air conditioner main body. A plurality of heat exchanging fins are placed under the tube banks and connected to a plurality of heat transfer tubes. Both the tube banks and the heat transfer tubes are supported by a pair of guide plates placed on opposed sides of both the tube banks and the heat transfer tubes. The tube banks include a plurality of small diameter tubes and a plurality of distribution manifolds. The manifolds are connected to bundles of small diameter tubes respectively.

摘要翻译： 一种用于可分离式空调的小型换热器，不仅节省电力，而且降低了成本。 热交换器具有设置在空调机主体的预定上部的管堤。 多个热交换翅片放置在管组下方并连接到多个传热管。 管组和传热管都由放置在管组和传热管的相对侧上的一对引导板支撑。 管组包括多个小直径管和多个分配歧管。 歧管分别连接到小直径管束。

公开(公告)号：US20100142893A1

公开(公告)日：2010-06-10

申请号：US12391075

申请日：2009-02-23

申请人： Beom-Hoan O ,  Dong-Jin Lee

发明人： Beom-Hoan O ,  Dong-Jin Lee

IPC分类号： G02B6/26

CPC分类号： G02B6/1225 ,  B82Y20/00

摘要： Disclosed herein is a photonic crystal waveguide inlet structure for improving coupling efficiency of a strip waveguide and a photonic crystal waveguide. The photonic crystal waveguide inlet structure includes an inlet region of the photonic crystal waveguide. The photonic crystal waveguide includes photonic crystals in which air holes are arranged in a triangle lattice shape in a dielectric, and a hybrid waveguide in which at least one of the air holes is removed, the hybrid waveguide spacing the inlet region apart from the strip waveguide.

摘要翻译： 本文公开了一种用于提高条形波导和光子晶体波导的耦合效率的光子晶体波导入口结构。 光子晶体波导入口结构包括光子晶体波导的入口区域。 光子晶体波导包括其中空气孔在电介质中以三角形格子形状布置的光子晶体和其中至少一个空气孔被去除的混合波导，该混合波导将入口区域与带状波导分开 。

公开(公告)号：US07317669B2

公开(公告)日：2008-01-08

申请号：US10894360

申请日：2004-07-20

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： G11B7/00

CPC分类号： G11B7/0953

摘要： A method and apparatus compensating for disc eccentricity includes extracting eccentricity data from a tracking error signal having one period, generated by a tracking servo, detecting parameter values of an eccentricity component extracted during the extraction of the eccentricity data and transforming a reference sine wave based on the detected parameter values of the eccentricity component. The eccentricity data is replaced with the transformed reference sine wave and the replaced eccentricity data is added to the tracking error signal to compensate for the disc eccentricity.

摘要翻译： 补偿盘偏心度的方法和装置包括从跟踪伺服产生的具有一个周期的跟踪误差信号中提取偏心数据，检测在提取偏心数据期间提取的偏心分量的参数值，并基于 检测到偏心分量的参数值。 偏心率数据被变换后的参考正弦波代替，替代的偏心数据被加到跟踪误差信号中，以补偿盘偏心。

公开(公告)号：US20070182462A1

公开(公告)日：2007-08-09

申请号：US11609660

申请日：2006-12-12

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： H03B1/00

CPC分类号： H03K17/0822 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H03K17/6872 ,  H03K19/018528

摘要： An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.

摘要翻译： 能够控制短路电流的输出驱动器包括驱动单元和驱动控制单元。 驱动单元响应于控制信号接收第一驱动信号和第二驱动信号，并产生输出信号。 驱动单元控制单元包括具有与驱动单元相同结构的驱动单元复制单元，并将由驱动单元复制单元产生的第一和第二驱动信号的输出复制信号与参考电压进行比较，并产生控制信号 在测试模式下第一和第二驱动信号的延迟。

公开(公告)号：US06707653B2

公开(公告)日：2004-03-16

申请号：US10251979

申请日：2002-09-23

申请人： Dong-Jin Lee ,  Ki-Whan Song

发明人： Dong-Jin Lee ,  Ki-Whan Song

IPC分类号： H02H900

CPC分类号： H01L27/0262

摘要： An electrostatic discharge (ESD) protection circuit includes an MOS transistor acting as a trigger for the circuit. A drain region of the MOS transistor is formed by an N-type heavily doped impurity region which overlaps an N-type well region. Further, a P-type heavily doped impurity region is formed in the N-type well region. The N-type and P-type heavily doped impurity regions are electrically connected to an input/output pad. The ESD protection circuit exhibits a reduced input capacitance at the pad, and a reduced breakdown voltage of the MOS transistor.

摘要翻译： 静电放电（ESD）保护电路包括用作电路触发器的MOS晶体管。 MOS晶体管的漏极区域与N型阱区域重叠的N型重掺杂杂质区域形成。 此外，在N型阱区中形成P型重掺杂杂质区。 N型和P型重掺杂杂质区域电连接到输入/输出焊盘。 ESD保护电路在焊盘处表现出降低的输入电容，并且降低了MOS晶体管的击穿电压。

公开(公告)号：US07821309B2

公开(公告)日：2010-10-26

申请号：US11977352

申请日：2007-10-24

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

摘要翻译： 延迟锁定环（DLL）电路具有延迟接收到的外部时钟信号以获得精细延迟时间的第一延迟线，然后输出第一内部时钟信号; 占空比校正单元，校正第一内部时钟信号的占空比，然后输出第二时钟信号; 第二延迟线，延迟所述第二时钟信号的粗略延迟时间，然后输出第二内部时钟信号; 以及相位检测和控制单元，其检测外部时钟信号和反馈的第二内部时钟信号的相位之间的差异，并且控制精细延迟时间和粗略延迟时间。 DLL电路通过使用不同类型的延迟单元执行粗略锁定和精细锁定，从而消耗少量的功率，并且坚固地承受PVT变量的抖动和变化。

公开(公告)号：US07586415B2

公开(公告)日：2009-09-08

申请号：US11553329

申请日：2006-10-26

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： G08B13/14

CPC分类号： G06K19/07749 ,  H01Q1/2225 ,  H01Q9/0407

摘要： A radio frequency identification (RFID) tag is provided including a lower antenna, an upper antenna, a RFID chip, and a spacer. The lower antenna has a coupling projection at one end. The upper antenna has a coupling groove at one end. The RFID chip contains information of an object which can be communicated with a reader device. One end of the RFID chip is coupled with the projection of the lower antenna and the other end is coupled with the groove of the upper antenna. The spacer is between the antennas to isolate the antennas electrically. The antennas are combined on both sides of the spacer in parallel. The RFID chip is connected with the antennas and fitted on a top side or a bottom side of the spacer so that active signals are transmitted through the antennas to send the information in the RFID chip to the reader device.

摘要翻译： 提供了包括下天线，上天线，RFID芯片和间隔器的射频识别（RFID）标签。 下天线在一端具有耦合突起。 上天线在一端具有耦合槽。 RFID芯片包含可与读取器设备通信的对象的信息。 RFID芯片的一端与下部天线的突起连接，另一端与上部天线的凹槽连接。 间隔物在天线之间，以电隔离天线。 天线在间隔物的两侧并联组合。 RFID芯片与天线连接并且安装在间隔物的顶侧或底侧，使得有源信号通过天线传输，以将RFID芯片中的信息发送到读取器设备。

公开(公告)号：US07477715B2

公开(公告)日：2009-01-13

申请号：US11623925

申请日：2007-01-17

申请人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

发明人： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

摘要： A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

摘要翻译： 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US20080285346A1

公开(公告)日：2008-11-20

申请号：US12219600

申请日：2008-07-24

申请人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

发明人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

IPC分类号： G11C16/04 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

摘要翻译： 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。