公开(公告)号：US20070279117A1

公开(公告)日：2007-12-06

申请号：US11769408

申请日：2007-06-27

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Samuel Ray ,  Wayne Utter

IPC分类号： H03K3/00

CPC分类号： G06F1/04

摘要： A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.

摘要翻译： 提供差分时钟信号门控方法和系统，提供具有与时钟信号的时序关系的时钟选通信号和到缓冲器差分对负载元件的差分对电流。 响应于门控信号脉冲将差分对电流从负载元件切换到缓冲差分对，门控信号脉冲与第一时钟信号脉冲相关，缓冲差分对缓冲在第一时钟信号脉冲之后立即和顺序发生的第二时钟信号脉冲 时钟信号脉冲和连续时钟信号脉冲作为缓冲时钟信号输出，所述输出包括多个脉冲，每个脉冲具有时钟信号幅度和时钟信号脉冲宽度。

公开(公告)号：US20070254613A1

公开(公告)日：2007-11-01

申请号：US11411662

申请日：2006-04-26

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman

IPC分类号： H04B7/00

CPC分类号： H03L7/18 ,  H03L7/0891

摘要： A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.

摘要翻译： 用于跟踪VCO校准的电路设计，方法和系统，而不需要如常规实现中的过度设计的分频器。 滤波器复位分量被添加到VCO的输入端。 在校准机构/过程中添加了一个处理步骤，该校准机构/过程使滤波器节点短路，并因此在从一个频带到下一个频带之前将VCO的频率居中。

公开(公告)号：US20050077936A1

公开(公告)日：2005-04-14

申请号：US10685022

申请日：2003-10-14

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus

IPC分类号： H03L7/10 ,  H03L7/00

CPC分类号： H03L7/10

摘要： Aspects for reducing jitter in a PLL of a high speed serial link are described. The aspects include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

摘要翻译： 描述了降低高速串行链路的PLL抖动的方面。 这些方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调节。 调节器控制电路进行检查和控制。

公开(公告)号：US20070096720A1

公开(公告)日：2007-05-03

申请号：US11262101

申请日：2005-10-28

申请人： Steven Clements ,  William Cornwell ,  Carrie Cox ,  Hayden Cranford ,  Vernon Norman

发明人： Steven Clements ,  William Cornwell ,  Carrie Cox ,  Hayden Cranford ,  Vernon Norman

IPC分类号： G01R31/28

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US20050046489A1

公开(公告)日：2005-03-03

申请号：US10650396

申请日：2003-08-28

申请人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus ,  Peter Seidel

发明人： Hayden Cranford ,  Stacy Garvin ,  Vernon Norman ,  Todd Rasmus ,  Peter Seidel

IPC分类号： H03L7/08 ,  H03L7/00

CPC分类号： H03L7/08 ,  H03L2207/06

摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

摘要翻译： 公开了一种用于锁相环的自适应电压调节器。 锁相环包括相位检测器，电荷泵，低通滤波器和压控振荡器，其中低通滤波器将控制电压输入到压控振荡器以产生输出时钟。 根据本文公开的方法和系统，自适应电压调节器耦合到低通滤波器的输出，用于在锁相环的正常操作期间感测控制电压，并且用于动态调整供电电压，即 响应于控制电压输入到压控振荡器，使得锁相环将控制电压保持在参考电压的预定范围内。

公开(公告)号：US20070047589A1

公开(公告)日：2007-03-01

申请号：US11211125

申请日：2005-08-24

申请人： Bobak Modaress-Razavi ,  Vernon Norman

发明人： Bobak Modaress-Razavi ,  Vernon Norman

IPC分类号： H04J3/06 ,  H04J3/04

CPC分类号： H03M9/00 ,  H04J3/0685

摘要： A serializer/deserializer (SERDES) receiver circuit designed to support multiple serial data rates (full, half, and quarter rates) based on user selection, while requiring substantially minimal amounts of additional logic and complexity within the core logic functions and analog circuits of a full rate SERDES. Over-sampled data from the analog block is provided to support each of the different rates, and the data is stored in three preliminary rate registers, one for full rate, one for half rate and one for quarter rate. In full rate mode, all samples coming from the analog circuits are utilized. In half rate and quarter rate modes, one out of every two samples and one out of every four samples is utilized, respectively. The selected samples are converted to parallel data by core logic functions, which are provided a single clock signal corresponding to the particular mode of operation.

摘要翻译： 串行器/解串器（SERDES）接收器电路，其设计用于基于用户选择来支持多个串行数据速率（全，半和四分之一速率），同时在核心逻辑功能和模拟电路中需要基本上最小量的附加逻辑和复杂性 全速SERDES。 提供来自模拟块的过采样数据以支持每个不同的速率，并且数据存储在三个初始速率寄存器中，一个用于全速率，一个一半速率，一个用于四分之一速率。 在全速率模式下，利用来自模拟电路的所有采样。 在半速率和四分之一速率模式下，分别利用了每两个样本中的一个和四个样本中的一个。 所选样本通过核心逻辑功能转换为并行数据，其被提供与特定操作模式对应的单个时钟信号。

公开(公告)号：US20050267705A1

公开(公告)日：2005-12-01

申请号：US10709805

申请日：2004-05-28

申请人： Jeanne Bickford ,  Vernon Norman ,  Michael Ouellette ,  Mark Styduhar ,  Brian Worth

发明人： Jeanne Bickford ,  Vernon Norman ,  Michael Ouellette ,  Mark Styduhar ,  Brian Worth

IPC分类号： G01R31/28 ,  G06F19/00 ,  H01L21/66

CPC分类号： G01R31/2831 ,  H01L22/14

摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. The predetermined distribution value is previously obtained based on a ground rule resistance. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer is then adjusted accordingly, and subsequent wafers running on the wafer manufacturing line are also adjusted according to the offset value.

摘要翻译： 公开了一种用于对在生产线上运行的晶片进行质量控制的方法。 初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。 然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。 记录实际分布值与预定分布值之间的差。 基于接地规则电阻预先获得预定分布值。 接下来，测量晶片内的一组设计测试结构的电阻。 设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。 然后相应地调节晶片内的可调节电阻电路的电阻，并且还根据偏移值来调整在晶片制造线上运行的后续晶片。