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公开(公告)号：US11651818B2
公开(公告)日：2023-05-16
申请号：US17443586
申请日：2021-07-27
Applicant: Kioxia Corporation
Inventor： Ryu Ogiwara , Daisaburo Takashima , Takahiko Iizuka
CPC classification number: G11C13/0028 , G11C13/004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C16/0433 , G11C16/3404
Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.
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公开(公告)号：US11373703B2
公开(公告)日：2022-06-28
申请号：US17183803
申请日：2021-02-24
Applicant: KIOXIA CORPORATION
Inventor： Sumiko Domae , Daisaburo Takashima
Abstract: During a writing operation to change a resistance of a part of a variable resistance material film facing a first word line, the semiconductor storage device applies a first voltage to the first word line, applies a second voltage to a second word line, and applies a third voltage to a third word line. The first, second, and third word lines are stacked above a substrate. The second word line is adjacent to the first word line in the stacking direction. The third word line is not adjacent to the first word line in the stacking direction.
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公开(公告)号：US12277989B2
公开(公告)日：2025-04-15
申请号：US18359355
申请日：2023-07-26
Applicant: Kioxia Corporation
Inventor： Ryu Ogiwara , Hidehiro Shiga , Daisaburo Takashima
Abstract: According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.
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Patent Agency Ranking
公开(公告)号：US12207480B2
公开(公告)日：2025-01-21
申请号：US17899898
申请日：2022-08-31
Applicant: KIOXIA CORPORATION
Inventor： Tomoki Chiba , Daisaburo Takashima , Hidehiro Shiga
Abstract: A variable resistance non-volatile memory includes a semiconductor substrate, a first electrode line extending in a first direction away from the semiconductor substrate, a second electrode line extending in the first direction parallel to the first electrode line, an insulating film between the first and second electrode lines, a variable resistance film formed on the first electrode line, a low electrical resistance layer formed on the variable resistance film and having a lower electrical resistance than the variable resistance film, a semiconductor film in contact with the low electrical resistance layer and the insulating film, and formed on opposite surfaces of the second electrode line, a gate insulator film extending in the first direction and in contact with the semiconductor film, and a voltage application electrode that extends in a second direction that crosses the first direction, and is in contact with the gate insulator film.
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公开(公告)号：US11972797B2
公开(公告)日：2024-04-30
申请号：US17679959
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Hidehiro Shiga , Daisaburo Takashima
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0038 , G11C13/0069
Abstract: A memory device includes a memory cell array including a select transistor and a plurality of memory cells connected in series, each memory cell including a cell transistor and a variable resistance layer connected in parallel. During a write operation, a voltage setting circuit is controlled to apply a first voltage to a selected word line and a second voltage to non-selected word lines. The time period for applying the first voltage to the selected word line starts later than the time period for applying the second voltage to the non-selected word lines and ends earlier than the time period for applying the second voltage to the non-selected word lines.
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公开(公告)号：US11744088B2
公开(公告)日：2023-08-29
申请号：US17495103
申请日：2021-10-06
Applicant: Kioxia Corporation
Inventor： Ryu Ogiwara , Daisaburo Takashima , Takahiko Iizuka
CPC classification number: H10B63/845 , G11C13/0004 , G11C13/004 , H10B63/34 , H10N70/231 , H10N70/8828 , G11C2213/71 , G11C2213/79
Abstract: According to one embodiment, a memory device includes: a first variable resistance layer; first and second semiconductor layers being in contact with the first variable resistance layer; a first word line; a second word line being adjacent to the first word line; and a third word line being adjacent to the first and second word lines with the first semiconductor layer, the first variable resistance layer, and the second semiconductor layer interposed therebetween, and provided between the first word line and the second word line. In the first variable resistance layer, a first region including a shortest path connecting the first word line and the third word line functions as a first memory cell, and a second region including a shortest path connecting the third word line and the second word line functions as a second memory cell.
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公开(公告)号：US11721371B2
公开(公告)日：2023-08-08
申请号：US17495747
申请日：2021-10-06
Applicant: Kioxia Corporation
Inventor： Ryu Ogiwara , Daisaburo Takashima , Takahiko Iizuka
CPC classification number: G11C7/065 , G11C5/06 , G11C7/1069 , G11C7/12 , G11C7/14
Abstract: According to one embodiment, a memory device includes: a plurality of memory cells stacked in a first direction orthogonal to a substrate and each including a memory element having at least three resistance states and a selector coupled in parallel to the memory element; a bit line electrically coupled to the memory cells and extending in a second direction intersecting the first direction; and a sense amplifier configured to compare a voltage of the bit line with a plurality of reference voltages and sense data stored in the memory cells.
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公开(公告)号：US11615840B2
公开(公告)日：2023-03-28
申请号：US17022580
申请日：2020-09-16
Applicant: Kioxia Corporation
Inventor： Ryu Ogiwara , Daisaburo Takashima , Takahiko Iizuka
Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.
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