公开(公告)号：US12211551B2

公开(公告)日：2025-01-28

申请号：US18177704

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Natsuki Sakaguchi ,  Takashi Maeda ,  Rieko Funatsuki ,  Hidehiro Shiga

IPC: G11C16/04 ,  G11C7/06 ,  G11C16/24

Abstract: A control circuit of a semiconductor memory device performs a write operation on a memory cell transistor of the semiconductor memory device by performing a first pulse application operation of lowering a threshold voltage of the memory cell transistor, a precharge operation, and then a second pulse application operation. In the precharge operation, in a state in which first and second select transistors connected to the memory cell transistor are turned on, a bit line connected to the memory cell transistor is charged by applying a ground voltage to a word line connected to a gate of the memory cell transistor and applying a voltage higher than the ground voltage to a source line. In the second pulse application operation, in a state in which the first select transistor is turned on and the second select transistor is turned off, a program voltage is applied to the word line.

公开(公告)号：US12144189B2

公开(公告)日：2024-11-12

申请号：US17939859

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Hidehiro Shiga ,  Daisaburo Takashima

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/80 ,  H10N70/00

Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.

公开(公告)号：US11967371B2

公开(公告)日：2024-04-23

申请号：US17806346

申请日：2022-06-10

Applicant: Kioxia Corporation

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Hidehiro Shiga

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

公开(公告)号：US12068031B2

公开(公告)日：2024-08-20

申请号：US17901239

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Jun Deguchi ,  Daisuke Miyashita ,  Atsushi Kawasumi ,  Hidehiro Shiga ,  Shinji Miyano ,  Shinichi Sasaki

IPC: G11C16/08 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

公开(公告)号：US11972798B2

公开(公告)日：2024-04-30

申请号：US17681680

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoki Chiba ,  Daisaburo Takashima ,  Hidehiro Shiga

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069

Abstract: A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.

公开(公告)号：US11955176B2

公开(公告)日：2024-04-09

申请号：US17459974

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro Shiga

IPC: G11C16/04 ,  G11C5/06 ,  G11C7/18 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C5/063 ,  G11C7/18 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A nonvolatile semiconductor storage device includes first and second semiconductor layers extending in a first direction and spaced apart in a second direction, first and second bit lines extending in the second direction and respectively arranged on opposite sides of the semiconductor layers in the first direction, first and second source lines extending in a third direction and respectively arranged on opposite sides of the semiconductor layers in the first direction, a first memory string including first and second select transistors connected to the first bit line and the first source line, respectively, a second memory string including third and fourth select transistors connected to the second bit line and the second source line, respectively, a first select gate line connected to gates of the first and fourth select transistors, and a second select gate line connected to gates of the second and third select transistors.

公开(公告)号：US11232843B2

公开(公告)日：2022-01-25

申请号：US17009376

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro Shiga ,  Takashi Maeda

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.

公开(公告)号：US12277989B2

公开(公告)日：2025-04-15

申请号：US18359355

申请日：2023-07-26

Applicant: Kioxia Corporation

Inventor： Ryu Ogiwara ,  Hidehiro Shiga ,  Daisaburo Takashima

IPC: G11C5/06 ,  G11C5/02 ,  H10B63/00

Abstract: According to one embodiment, in a semiconductor memory device, multiple first memory cells are connected in parallel between a first local bit line and a local source line. Multiple second memory cells are connected in parallel between a second local bit line and the local source line. Each of the multiple first memory cells includes a first cell transistor and a first resistance change element connected in series. Each of the multiple second memory cells includes a second cell transistor and a second resistance change element connected in series. A first selection gate line extends in a second direction across multiple cell blocks arranged in the second direction. A second selection gate line is placed on the opposite side of the first selection gate line with the local source line interposed therebetween. The second selection gate line extends in the second direction across multiple cell blocks arranged in the second direction.

公开(公告)号：US11282559B1

公开(公告)日：2022-03-22

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika Tanaka ,  Masumi Saitoh ,  Takashi Maeda ,  Rieko Funatsuki ,  Hidehiro Shiga

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

公开(公告)号：US11049573B2

公开(公告)日：2021-06-29

申请号：US16802471

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Rieko Funatsuki ,  Takashi Maeda ,  Hidehiro Shiga ,  Hiroshi Maejima

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor storage device includes a first memory cell and a second memory cell which are connected to each other in series, a first word line which is connected to the first memory cell, a second word line which is connected to the second memory cell, and a control circuit. The control circuit is configured to charge a first node while applying a second voltage to the second word line and a first voltage to the first word line, to charge a second node on the basis of a voltage of the charged first node, to discharge the second node while applying the second voltage to the second word line and a third voltage to the first word line, and to read data from the first memory cell on the basis of voltages of the charged and discharged second node.