公开(公告)号：US20250031378A1

公开(公告)日：2025-01-23

申请号：US18908458

申请日：2024-10-07

Applicant: Kioxia Corporation

Inventor： Go OIKE

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50 ,  H10B53/20

Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

公开(公告)号：US20230209833A1

公开(公告)日：2023-06-29

申请号：US18179533

申请日：2023-03-07

Applicant: KIOXIA CORPORATION

Inventor： Go OIKE

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.

公开(公告)号：US20230113904A1

公开(公告)日：2023-04-13

申请号：US18065298

申请日：2022-12-13

Applicant: Kioxia Corporation

Inventor： Go OIKE ,  Hanae ISHIHARA

IPC: H01L29/792

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

公开(公告)号：US20230082971A1

公开(公告)日：2023-03-16

申请号：US17686108

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Hideo WADA ,  Hiroyuki YAMASAKI ,  Masahisa SONODA ,  Go OIKE

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device includes a first substrate, a first insulating film disposed on the first substrate, and a semiconductor layer disposed on the first insulating film. The semiconductor device further includes a metal layer with a first portion and a second portion. The first portion is disposed on the semiconductor layer, and the second portion includes a bonding pad and is disposed on the first insulating film without the semiconductor layer interposed between the second portion and the first insulating film.

公开(公告)号：US20220157851A1

公开(公告)日：2022-05-19

申请号：US17665979

申请日：2022-02-07

Applicant: KIOXIA CORPORATION

Inventor： Go OIKE ,  Tsuyoshi SUGISAKI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  G11C5/06 ,  H01L27/11565 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11519

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

公开(公告)号：US20210265387A1

公开(公告)日：2021-08-26

申请号：US17009005

申请日：2020-09-01

Applicant: Kioxia Corporation

Inventor： Go OIKE

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C7/18

Abstract: A semiconductor storage device according to an embodiment includes a stacked body in which a conductive layer and an insulating layer are stacked alternately in a first direction, a plurality of columnar bodies that extend in the first direction inside the stacked body and each include a semiconductor body, a plurality of charge storage films that are disposed between at least one of a plurality of the conductive layers and each of a plurality of the semiconductor bodies, a plurality of bit lines that extend above the stacked body in a second direction intersecting the first direction, an interlayer insulating layer that is between the stacked body and the bit lines, and contacts each of which penetrates the interlayer insulating layer and is electrically connected to one of the plurality of bit lines, in which the contacts have a first contact that is connected to one of the columnar bodies and a second contact that is connected to a plurality of the columnar bodies.