公开(公告)号：US08120110B2

公开(公告)日：2012-02-21

申请号：US12188381

申请日：2008-08-08

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC: H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract translation: 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。

公开(公告)号：US20120025881A1

公开(公告)日：2012-02-02

申请号：US12845390

申请日：2010-07-28

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhenrong Jin ,  Francis F. Szenher

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/22

Abstract: A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

Abstract translation: 一种方法包括通过向PLL电路的电荷泵的输出施加注入电流来相移锁相环（PLL）电路的输出信号。 电路包括：第一锁相环（PLL）电路和参考相同时钟的第二PLL电路; 相位检测器电路，检测第一PLL电路的输出信号和第二PLL电路的输出信号之间的相位差; 以及可调电流源，其基于相位检测器电路的输出将注入电流施加到第一PLL电路和第二PLL电路中的至少一个。

公开(公告)号：US20110073858A1

公开(公告)日：2011-03-31

申请号：US12566726

申请日：2009-09-25

Applicant: Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L21/76898

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

Abstract translation: 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括第一TSV，电连接到第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

公开(公告)号：US07915158B2

公开(公告)日：2011-03-29

申请号：US12144071

申请日：2008-06-23

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/0248

Abstract: A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.

Abstract translation: 描述形成片上高频静电放电装置的方法。 在一个实施例中，提供具有多金属层布线的晶片。 该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到 在第二介电层中分别有一个以上的电极。 多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。 至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。 在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

公开(公告)号：US20100308922A1

公开(公告)日：2010-12-09

申请号：US12477945

申请日：2009-06-04

Applicant: Kai D. Feng ,  Anjali R. Malladi ,  Pradeep Thiagarajan

Inventor： Kai D. Feng ,  Anjali R. Malladi ,  Pradeep Thiagarajan

IPC: H03L7/00

CPC classification number: H03L7/099

Abstract: Circuits and methods for automated real-time tuning of wide range frequency/delay voltage controlled oscillators (VCO) using a reset mechanism, to account for run-time variations such as power supply, temperature, reference clock frequency and input slew drift etc is described. It finds extensive applications in wide range, multi frequency band phase and delay locked loops. In one embodiment, an automated Jump-Down band switching structure and method for use in VCOs with a plurality of frequency bands is described. This involves monitoring the VCO's analog control voltage signal until it reaches a predetermined lower limit, at which time band switching to an overlapping lower frequency band is triggered by an internally generated reset signal, while simultaneously charging the analog control voltage to a limit in a pre-determined range of the lower band, to avoid phase detector malfunctions in the PLL/DLL system at lower control voltages during band switch.

Abstract translation: 描述使用复位机制对宽范围频率/延迟电压控制振荡器（VCO）进行自动实时调谐的电路和方法，以解决运行时间变化，如电源，温度，参考时钟频率和输入摆幅漂移等。 。 它广泛应用于宽范围，多频段相位和延迟锁定环路。 在一个实施例中，描述了一种在具有多个频带的VCO中使用的自动跳跃频带切换结构和方法。 这涉及监视VCO的模拟控制电压信号，直到其达到预定的下限，在此时间段切换到重叠的较低频带由内部产生的复位信号触发，同时将模拟控制电压充电到预先的限制 确定低频段的范围，以避免频段切换期间较低控制电压下PLL / DLL系统中的相位检测器故障。

公开(公告)号：US07733137B2

公开(公告)日：2010-06-08

申请号：US11873010

申请日：2007-10-16

Applicant: Kai D. Feng

Inventor： Kai D. Feng

IPC: H03L7/06

CPC classification number: H03L7/1974 ,  H03L7/0891

Abstract: A design structure including a system. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached.

Abstract translation: 包括系统的设计结构。 该系统包括分数N锁相环（PLL）。 PLL包括PLL输入和PLL输出。 分数N PLL还包括多路复用器。 多路复用器包括电耦合到PLL输入的多路复用器输出。 多路复用器还包括M个多路复用器输入，M是大于1的整数。通过从参考频率中选择一个参考频率，两个或多个参考频率被施加到多路复用器的输入端，可以达到低分支。

公开(公告)号：US20100038750A1

公开(公告)日：2010-02-18

申请号：US12191385

申请日：2008-08-14

Applicant: David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

Inventor： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

IPC: H01L29/92 ,  G06F17/50

CPC classification number: H01L29/66181 ,  H01L29/945

Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.

Abstract translation: 半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。

公开(公告)号：US20090316313A1

公开(公告)日：2009-12-24

申请号：US12144084

申请日：2008-06-23

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

IPC: H02H9/00 ,  G06F17/50

CPC classification number: G06F17/5068 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

Abstract translation: 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。 每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。 所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

公开(公告)号：US20090107220A1

公开(公告)日：2009-04-30

申请号：US11926241

申请日：2007-10-29

Applicant: Fen Chen ,  Kai D. Feng

Inventor： Fen Chen ,  Kai D. Feng

IPC: G01N25/56

CPC classification number: G01N27/223

Abstract: A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.

Abstract translation: 一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。 湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。 水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

公开(公告)号：US07489038B2

公开(公告)日：2009-02-10

申请号：US11220433

申请日：2005-09-07

Applicant: Elie Awad ,  Mariette A. Awad ,  Kai D. Feng

Inventor： Elie Awad ,  Mariette A. Awad ,  Kai D. Feng

IPC: H01L23/48

CPC classification number: H01L24/02 ,  H01L23/562 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025

Abstract: A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.

Abstract translation: 一种半导体结构，包括：基板，包括第一层，所述第一层包括具有第一弹性模量的第一材料; 包括导体并形成在所述基板内的第一结构，所述第一结构具有上表面; 以及靠近所述第一结构并且在所述第一层内的应力转向结构，所述应力转向结构在向所述第一结构施加物理载荷时在所述第一结构的上表面处提供低机械应力区域，其中所述低机械应力区域 包括低于应力转移结构保护区域的应力值。 应力转向结构包括具有小于第一弹性模量的第二弹性模量的第二材料，第二材料选择性地形成在第一结构的上表面上，用于转移由施加到第一结构的物理负载产生的机械应力。