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11.发明申请INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME 有权具有降低硅氧烷接触电阻的上升源排水装置的集成电路及其制造方法公开(公告)号：US20130207189A1
公开(公告)日：2013-08-15
申请号：US13852103
申请日：2013-03-28
IPC分类号： H01L29/78
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译： 结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。 栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。 该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。 第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。 每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。 还公开了制造该结构的方法。
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公开(公告)号：US20130082328A1
公开(公告)日：2013-04-04
申请号：US13251783
申请日：2011-10-03
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/66772 , H01L29/7849 , H01L29/78603 , H01L29/78654
摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.
摘要翻译： 公开了包括应激源的晶体管器件。 一个这样的晶体管器件包括沟道区，电介质层和半导体衬底。 沟道区域被配置为在源极区域和漏极区域之间提供导电沟道。 此外，电介质层在沟道区下方，并被配置为使沟道区电绝缘。 此外，半导体衬底在沟道区域下方和介电层下方包括在半导体衬底的顶表面处的位错缺陷，其中位错缺陷共同定向以在沟道区域施加压缩应变，使得载流子 渠道区域的移动性得到增强。
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13.发明授权公开(公告)号：US08338260B2
公开(公告)日：2012-12-25
申请号：US12760250
申请日：2010-04-14
IPC分类号： H01L21/336
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。
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公开(公告)号：US08318574B2
公开(公告)日：2012-11-27
申请号：US12847208
申请日：2010-07-30
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。
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公开(公告)号：US20120286364A1
公开(公告)日：2012-11-15
申请号：US13104542
申请日：2011-05-10
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/0727 , H01L21/823418 , H01L21/84 , H01L27/0629 , H01L27/1203
摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.
摘要翻译： 一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层 在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层 使用第二外延生长工艺在第一二极管层上。
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16.发明申请STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权具有单个间距的垂直源/源压应力的应变薄体CMOS器件公开(公告)号：US20120261757A1
公开(公告)日：2012-10-18
申请号：US13531053
申请日：2012-06-22
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。
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公开(公告)号：US20120261754A1
公开(公告)日：2012-10-18
申请号：US13086459
申请日：2011-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0603 , H01L29/1054 , H01L29/4236 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
摘要翻译： 公开了用于制造具有凹陷沟道和突然结的MOSFET的MOSFET和方法。 该方法包括在虚拟门就位的情况下创建源极和漏极扩展。 源极/漏极延伸部分产生与硅衬底的扩散结。 该方法通过去除伪栅极并蚀刻硅衬底中的凹槽来继续。 凹部与源极和漏极结的至少一部分相交。 然后，通过生长硅膜以至少部分地填充凹部而形成通道。 该通道与源极和漏极具有尖锐的结，而沟道下方的未蚀刻的硅具有与源极和漏极的扩散结。 因此，可以产生在相同晶体管中具有两个结区的尖锐和扩散的MOSFET。
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公开(公告)号：US20120235239A1
公开(公告)日：2012-09-20
申请号：US13049491
申请日：2011-03-16
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/823814 , H01L21/823878 , H01L29/7839
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触 并且在与栅极结构的漏极侧相邻的半导体衬底上。 因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。
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公开(公告)号：US20120068267A1
公开(公告)日：2012-03-22
申请号：US12886881
申请日：2010-09-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
IPC分类号： H01L29/786 , H01L21/762
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.
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公开(公告)号：US20120049284A1
公开(公告)日：2012-03-01
申请号：US12861976
申请日：2010-08-24
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译： 在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一 厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。
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