公开(公告)号：US6054728A

公开(公告)日：2000-04-25

申请号：US54946

申请日：1998-04-03

申请人： Yuichi Harada ,  Noriyuki Iwamuro ,  Tadayoshi Iwaana

发明人： Yuichi Harada ,  Noriyuki Iwamuro ,  Tadayoshi Iwaana

IPC分类号： H01L29/74 ,  H01L29/06 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/0692 ,  H01L29/7455 ,  H01L29/749

摘要： An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. The thyristor further includes a first main electrode that contacts with both the first base region and the first-conductivity-type source region, a second-conductivity-type emitter layer formed on the other surface of the first-conductivity-type base layer, a second main electrode that contacts with the second-conductivity-type emitter layer, a gate electrode connected to the gate electrode layer; and an insulating film covering entire surface areas of the second second-conductivity-type base region and the first-conductivity-type emitter region. In this insulated gate thyristor, an exposed surface portion of the first second-conductivity-type base region that is interposed between the first-conductivity-type base layer and the first-conductivity-type source region has a smaller width than an exposed surface portion of the second second-conductivity-type base region interposed between the first-conductivity-type base layer and the first-conductivity-type emitter region.

摘要翻译： 提供了一种绝缘栅晶闸管，其包括：第一导电型基极层，形成在基极层中的第一和第二第二导电型基极区域，形成在第一基极区域中的第一导电型源极区域， 形成在第二基极区域中的第一导电型发射极区域和形成在第一基极区域上的栅极绝缘膜上的栅极电极层，第一导电型基极层和第二基极区域， 导电型源极区域和第一导电型发射极区域。 晶闸管还包括与第一基极区域和第一导电型源极区域接触的第一主电极，形成在第一导电型基极层的另一个表面上的第二导电型发射极层， 与第二导电型发射极层接触的第二主电极，连接到栅电极层的栅电极; 以及覆盖所述第二第二导电型基极区域和所述第一导电型发射极区域的整个表面区域的绝缘膜。 在该绝缘栅极晶闸管中，介于第一导电型基极层和第一导电型源极区域之间的第一第二导电型基极区域的露出面部分的宽度比露出面部分 位于第一导电型基极层和第一导电型发射极区域之间的第二第二导电型基极区域。

公开(公告)号：US5991532A

公开(公告)日：1999-11-23

申请号：US593918

申请日：1996-01-30

申请人： Yuichi Harada

发明人： Yuichi Harada

IPC分类号： H04L29/02 ,  G06F9/455 ,  H04L12/28 ,  H04Q3/00

CPC分类号： H04L12/5601 ,  H04L2012/5665

摘要： A method that converts multimegabit-rate data into asynchronous transfer mode ATM cells and vice versa which are utilized in a switching system. The method includes determining whether the data is effective or ineffective in accordance with a portion of the data. Converting the data into the ATM cells when the data is determined to be effective. Disregarding the data when the data is determined to be ineffective. The method can be realized by an ATM interface converting unit connected with the switching system and a service interface unit. The service interface unit includes at least one of a switched multimegabit data services interface unit, a frame relay interface unit or a digital signal interface unit.

摘要翻译： 一种将多比特率数据转换为异步传输模式ATM信元的方法，反之亦然，在交换系统中被使用。 该方法包括根据数据的一部分确定数据是有效还是无效。 当数据被确定为有效时，将数据转换成ATM信元。 当数据被确定为无效时忽略数据。 该方法可以通过与交换系统连接的ATM接口转换单元和服务接口单元来实现。 服务接口单元包括交换多千兆位数据业务接口单元，帧中继接口单元或数字信号接口单元中的至少一个。

公开(公告)号：US5006003A

公开(公告)日：1991-04-09

申请号：US393810

申请日：1989-08-15

申请人： Yuichi Harada

发明人： Yuichi Harada

IPC分类号： B41J35/14 ,  B41J35/22

CPC分类号： B41J35/22

摘要： Disclosed is a typewriter wherein a ribbon holder mounted on a carriage movable along a platen holds both a print ribbon and a correction ribbon thereon and is displaceable between its first lift position for facing the print ribbon to a print point on the platen and its second lift position for facing the correction ribbon to said print point.The disclosed typewriter is provided with lift means for displacing the ribbon holder between its first and second lift position, detecting means for detecting the lift position of the ribbon holder, and control means for controlling the lift means to displace the ribbon holder in response to the result of detection of the detecting means, thereby the possibility of errorneous initial printing is eliminated, which may occur when a power supply is once turned off during a correcting action with a correction ribbon and then is turned on again to perform a normal print operation.

公开(公告)号：US4871274A

公开(公告)日：1989-10-03

申请号：US137767

申请日：1987-12-24

申请人： Yuichi Harada

发明人： Yuichi Harada

IPC分类号： B41J35/14 ,  B41J35/22

CPC分类号： B41J35/22

摘要： Disclosed is a typewriter wherein a ribbon holder mounted on a carriage movable along a platen holds both a print ribbon and a correction ribbon thereon and is displaceable between its first lift position for facing the print ribbon to a print point on the platen and its second lift position for facing the correction ribbon to said print point.The disclosed typewriter is provided with lift means for displacing the ribbon holder between its first and second lift position, detecting means for detecting the lift position of the ribbon holder, and control means for controlling the lift means to displace the ribbon holder in response to the result of detection of the detecting means, thereby the possibility of errorneous initial printing is eliminated, which may occur when a power supply is once turned off during a correcting action with a correction ribbon and then is turned on again to perform a normal print operation.

公开(公告)号：US09184230B2

公开(公告)日：2015-11-10

申请号：US14006548

申请日：2012-04-06

申请人： Yuichi Harada ,  Shinsuke Harada ,  Yasuyuki Hoshi ,  Noriyuki Iwamuro

发明人： Yuichi Harada ,  Shinsuke Harada ,  Yasuyuki Hoshi ,  Noriyuki Iwamuro

IPC分类号： H01L29/15 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

CPC分类号： H01L29/0615 ,  H01L29/0626 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7808 ,  H01L29/7827

摘要： A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer.

摘要翻译： 碳化硅垂直场效应晶体管包括第一导电型碳化硅衬底; 形成在第一导电型碳化硅衬底的表面上的低浓度第一导电型碳化硅层; 选择性地形成在第一导电型碳化硅层的表面上的第二导电型区域; 形成在第二导电型区域中的第一导电型源极区域; 形成在第二导电型区域中的第一导电型源极区域之间的高浓度第二导电型区域; 与高浓度第二导电型区域电连接的源电极和第一导电型源极区域; 由形成在相邻的第二导电型区域的第一导电型源极区域形成在第二导电型区域和第一导电型碳化硅层上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及在第一导电型碳化硅衬底的背侧上的漏电极，其中雪崩产生单元设置在第二导电型区域和第一导电型碳化硅层之间。

公开(公告)号：US20110099673A1

公开(公告)日：2011-04-28

申请号：US12994581

申请日：2008-06-27

申请人： Nahoko Kasai ,  Yuichi Harada ,  Chandra Sekar Ramanujan

发明人： Nahoko Kasai ,  Yuichi Harada ,  Chandra Sekar Ramanujan

IPC分类号： G01Q70/02 ,  G01Q90/00

CPC分类号： G01Q30/20

摘要： It is an object of the invention to provide a stage for scanning probe microscopy that can be used in any kind of SPM and can effectively irradiate light to a sample and a solution near the sample without irradiated light blocked by a cantilever. The stage for scanning probe microscopy of the invention is a stage for scanning probe microscopy for fixing a sample substrate that mounts a sample to be observed thereon and has optical transparency and includes an opening that is provided below a portion where the sample substrate is fixed and that has an opening area included within the sample substrate in plan view. Light is radiated from a bottom surface of the sample substrate onto the sample through the opening.

摘要翻译： 本发明的目的是提供一种用于扫描探针显微镜的阶段，该阶段可用于任何种类的SPM，并能有效地将样品和样品附近的溶液照射，而不受悬臂阻挡的照射光。 本发明的扫描探针显微镜的平台是用于扫描探针显微镜以固定安装要观察的样品的样品基底并具有光学透明性的阶段，并且包括设置在样品基板固定的部分下方的开口， 其在平面图中具有包含在样品基板内的开口区域。 光通过开口从样品基底的底表面辐射到样品上。

公开(公告)号：US07405913B2

公开(公告)日：2008-07-29

申请号：US10800013

申请日：2004-03-15

申请人： Hiroshi Tobisaka ,  Tatsuhiko Fujihira ,  Shin Kiuchi ,  Yoshiaki Minoya ,  Takeshi Ichimura ,  Naoki Yaezawa ,  Ryu Saitou ,  Shouichi Furuhata ,  Yuichi Harada

发明人： Hiroshi Tobisaka ,  Tatsuhiko Fujihira ,  Shin Kiuchi ,  Yoshiaki Minoya ,  Takeshi Ichimura ,  Naoki Yaezawa ,  Ryu Saitou ,  Shouichi Furuhata ,  Yuichi Harada

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device in includes a transistor and a surge absorption element such as Zener diode, that are formed on the same substrate and connected in parallel. The surge absorption element has a resistance during breakdown operation that is smaller than the resistance of the surge absorption element during breakdown operation of the transistor. In addition, the secondary breakdown current of the surge absorption element is larger than the secondary breakdown current of the transistor. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the surge absorption element and is limited to a voltage equal to or less than the breakdown voltage of the transistor, which would otherwise be destroyed.

摘要翻译： 一种半导体器件包括晶体管和诸如齐纳二极管的浪涌吸收元件，其形成在同一衬底上并联连接。 浪涌吸收元件在击穿操作期间具有小于在晶体管的击穿操作期间浪涌吸收元件的电阻的电阻。 此外，浪涌吸收元件的次级击穿电流大于晶体管的次级击穿电流。 在施加高ESD电压和高浪涌电压时，ESD和浪涌的能量被浪涌吸收元件的操作吸收并且被限制在等于或小于晶体管的击穿电压的电压，否则将是 被毁了

公开(公告)号：US06469344B2

公开(公告)日：2002-10-22

申请号：US09461264

申请日：1999-12-15

申请人： Noriyuki Iwamuro ,  Yuichi Harada

发明人： Noriyuki Iwamuro ,  Yuichi Harada

IPC分类号： H01L2976

CPC分类号： H01L29/7397

摘要： A semiconductor device is provided which includes a first p base region and a second p base region formed in one of opposite surface of a high-resistance n base region, a p collector region formed on the other surface of the n base region, an n emitter region formed in a surface layer of the first p base region, and a groove formed in the n base region between the first and second p base regions, to provide a trench gate electrode portion. The first and second p base regions are formed alternately in the Z-axis direction with certain spacing therebetween. The second p base region is held in a floating state in terms of the potential, thus assuring a reduced ON-resistance, and a large quantity of carriers present in the vicinity of the surface of the second p base region are quickly drawn away through a p channel upon turn-off, so that the turn-off time is reduced.

摘要翻译： 提供一种半导体器件，其包括形成在高电阻n基极区域的相对表面之一中的第一p基极区域和第二p基极区域，形成在n基极区域的另一个表面上的p1集电极区域，n发射极 形成在第一p基区域的表面层中的区域，以及形成在第一和第二p基极区域之间的n基极区域中的沟槽，以提供沟槽栅极电极部分。 第一和第二p基区域在Z轴方向上交替地形成，其间具有一定间隔。 第二p基区域根据电位保持在浮置状态，从而确保降低的导通电阻，并且存在于第二p基区域表面附近的大量载流子通过ap迅速地被吸走 通道关闭，从而减少关机时间。

公开(公告)号：US5981984A

公开(公告)日：1999-11-09

申请号：US951863

申请日：1997-10-16

申请人： Tadayoshi Iwaana ,  Yuichi Harada ,  Noriyuki Iwamuro

发明人： Tadayoshi Iwaana ,  Yuichi Harada ,  Noriyuki Iwamuro

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/739

CPC分类号： H01L29/749 ,  H01L29/7455

摘要： An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region. The thyristor further includes a gate electrode layer formed on an insulating film over the first second-conductivity-type base region, an exposed portion of the first-conductivity-type base layer and the second second-conductivity-type base region, a first main electrode that contacts both the first second-conductivity-type base layer and first-conductivity-type source region, a second-conductivity-type emitter layer formed on the first-conductivity-type base layer, a second main electrode that contacts the second-conductivity-type emitter layer, a gate electrode that contacts the gate electrode layer, and an insulating film covering entire areas of surfaces of the second second-conductivity-type base region and first-conductivity-type emitter region. In this insulated gate thyristor, the first-conductivity-type base layer includes a locally narrowed portion which is interposed between the first and second second-conductivity-type base regions.

摘要翻译： 绝缘栅晶闸管包括第一导电型基极层，其具有形成在第一导电型基极层的表面层中的高电阻率，第一和第二第二导电型基极区域，第一导电型源极 形成在第一第二导电型基极区域的表面层中的第一导电型发射极区域和形成在第二第二导电型基极区域的表面层中的第一导电型发射极区域。 所述晶闸管还包括形成在所述第一第二导电型基极区域上的绝缘膜上的栅极电极层，所述第一导电型基极层和所述第二第二导电型基极区域的露出部分， 电极，其与第一第二导电型基极层和第一导电型源极区域接触;第二导电型发射极层，形成在第一导电型基极层上;第二主电极， 导电型发射极层，与栅极电极层接触的栅极电极以及覆盖第二第二导电型基极区域和第一导电型发射极区域的整个表面的绝缘膜。 在该绝缘栅极晶闸管中，第一导电型基极层包括介于第一和第二第二导电型基极区域之间的局部变窄部分。

公开(公告)号：US20120299108A1

公开(公告)日：2012-11-29

申请号：US13516102

申请日：2011-01-28

申请人： Yuichi Harada ,  Tatsuya Naito ,  Yoshiaki Toyoda

发明人： Yuichi Harada ,  Tatsuya Naito ,  Yoshiaki Toyoda

IPC分类号： H01L27/088

CPC分类号： H01L21/84 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/1203 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/861 ,  H01L2224/48463 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： By connecting a protection diode (71) wherein p-anode layers (21) and n-cathode layers (22) are alternately formed in a polysilicon layer, and p-n junctions (74) that are in a reverse blocking state when there is a forward bias are alternately short circuited with a metal film (53), to a power semiconductor element (IGBT (72)), it is possible to achieve a balance between a high breakdown capability and a smaller chip area, a rise of breakdown voltage is suppressed even when a clamping voltage is repeatedly applied, and furthermore, it is possible to prevent destruction caused by a negative surge voltage input into a gate terminal (G).

摘要翻译： 通过连接其中在多晶硅层中交替形成p阳极层（21）和n-阴极层（22）的保护二极管（71）和当存在向前的方向时处于反向阻塞状态的pn结（74） 偏置与金属膜（53）交替地短路到功率半导体元件（IGBT（72）），可以实现高击穿能力和较小芯片面积之间的平衡，抑制击穿电压的上升 即使重复施加钳位电压，此外，可以防止由输入到栅极端子（G）的负浪涌电压引起的破坏。