公开(公告)号：US20070183552A1

公开(公告)日：2007-08-09

申请号：US11346903

申请日：2006-02-03

申请人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

发明人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0995

摘要： A clock and data recovery circuit including a first circuit and a second circuit. The first circuit is configured to receive a clock signal and a phase control signal and to lock onto the clock signal and provide a cleaned clock signal. The second circuit is configured to receive a data signal and the cleaned clock signal and to sample the data signal via the cleaned clock signal and provide the phase control signal. The first circuit adjusts the phase of the cleaned clock signal based on the phase control signal.

摘要翻译： 一种包括第一电路和第二电路的时钟和数据恢复电路。 第一电路被配置为接收时钟信号和相位控制信号，并锁定到时钟信号上并提供清洁的时钟信号。 第二电路被配置为接收数据信号和清除的时钟信号，并且经由清除的时钟信号对数据信号进行采样并提供相位控制信号。 第一个电路基于相位控制信号来调整清除的时钟信号的相位。

公开(公告)号：US20060023827A1

公开(公告)日：2006-02-02

申请号：US10530852

申请日：2002-10-10

申请人： Anthony Sanders ,  Edoardo Prete

发明人： Anthony Sanders ,  Edoardo Prete

IPC分类号： H03D3/24 ,  H03L7/06

CPC分类号： H03L7/087 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033

摘要： The invention provides a clock signal extraction device for extracting a clock signal from a periodic data signal, comprising a phase detector (104, 106) for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal; and a clock generator (110, 112) for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. The invention further provides a method for extracting a clock signal from a periodic data signal.

摘要翻译： 本发明提供了一种用于从周期性数据信号中提取时钟信号的时钟信号提取装置，包括用于检测所述数据信号的上升沿与上升沿时钟信号之间的第一相位差的相位检测器（104,106），并用于检测 所述数据信号的下降沿与下降沿时钟信号之间的第二相位差; 以及时钟发生器（110,112），用于产生所述上升沿时钟信号，使得所述第一相位差最小化，用于产生所述下降沿时钟信号，使得所述第二相位差最小化，并且用于根据 所述第一相位差和所述第二相位差。 本发明还提供了一种从周期性数据信号中提取时钟信号的方法。

公开(公告)号：US08553754B2

公开(公告)日：2013-10-08

申请号：US12973242

申请日：2010-12-20

申请人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

发明人： Ramon Mangaser ,  Shefali Walia ,  Edoardo Prete ,  Jonathan P. Dowling ,  Gerald R. Talbot ,  Sharad N. Vittal

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03878 ,  H04L25/03057

摘要： A decision feedback equalization (DFE) receiver and method are provided. The DFE receiver is configured to sample data bits from a data bus. The DFE receiver includes a data sampler configured to sample a current data bit from the data bus using one of a first, second and third voltage reference. The DFE receiver also includes multiplexing logic configured to select one of the first, second and third voltage references based on a prior data bus level. The wherein the first voltage reference is selected if the prior data bus level was a logic zero. The second voltage reference is selected if the prior data bus level was a logic one. The third voltage reference is selected if the prior data bus level was tri-state.

摘要翻译： 提供了一种判决反馈均衡（DFE）接收机和方法。 DFE接收器配置为从数据总线采样数据位。 DFE接收器包括数据采样器，其被配置为使用第一，第二和第三参考电压之一从数据总线采样当前数据位。 DFE接收机还包括被配置为基于先前的数据总线电平来选择第一，第二和第三电压基准之一的多路复用逻辑。 其中如果先前数据总线电平为逻辑0，则选择第一参考电压。 如果先前的数据总线电平为逻辑1，则选择第二个参考电压。 如果先前的数据总线电平为三态，则选择第三个参考电压。

公开(公告)号：US07420430B2

公开(公告)日：2008-09-02

申请号：US11194494

申请日：2005-08-01

申请人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

发明人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

IPC分类号： H03B28/00

CPC分类号： H03K5/13 ,  H03K2005/00286 ,  H04L7/0025

摘要： Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals.A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

摘要翻译： 用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置。 提供了一种用于产生输出时钟信号（o）的方法和装置，其中具有彼此具有预定相位关系的多个输入时钟信号（s，c）以相应的加权因子（A，1） -A），并且其中加上加权输入时钟信号（s'，c'），以便产生加法时钟信号（i）。 累加时钟信号（i）被积分在积分器（8）中并且可选地被放大以产生输出时钟信号（o）。 具有可调相位关系的输出时钟信号（o）可以通过这样一种方式产生，其中对输入时钟信号的要求不那么严格。

公开(公告)号：US20080024215A1

公开(公告)日：2008-01-31

申请号：US11494848

申请日：2006-07-28

申请人： Karthik Gopalakrishnan ,  Luca Ravezzi ,  Sivaraman Chokkalingam ,  Edoardo Prete ,  Hamid Partovi

发明人： Karthik Gopalakrishnan ,  Luca Ravezzi ,  Sivaraman Chokkalingam ,  Edoardo Prete ,  Hamid Partovi

IPC分类号： H03F3/04

CPC分类号： H03M1/1245

摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

摘要翻译： 数据采样器，包括第一级和第二级。 第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。 第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。 第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。

公开(公告)号：US20070183553A1

公开(公告)日：2007-08-09

申请号：US11346905

申请日：2006-02-03

申请人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

发明人： Anthony Sanders ,  Dirk Scheideler ,  Edoardo Prete

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/093

摘要： A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

摘要翻译： 时钟和数据恢复电路包括相位检测器，被配置为将数据信号的相位与采样时钟的相位进行比较以提供相位误差信号;增益级，被配置为对相位误差信号施加增益以提供放大 相位误差信号，以及被配置为对放大的相位误差信号进行滤波以提供相位校正信号的滤波器。 该电路包括：增益控制器，被配置为响应于相位校正信号调整增益级的增益;以及时钟发生器，被配置为基于相位校正信号提供采样时钟。

公开(公告)号：US20070177702A1

公开(公告)日：2007-08-02

申请号：US11338176

申请日：2006-01-23

申请人： Anthony Sanders ,  Matthias Schobinger ,  Edoardo Prete ,  Norbert Neurohr ,  Johannes Sturm ,  Eva Tatschl-Unterberger ,  Nicola Dadalt ,  Daniele Gardellini

发明人： Anthony Sanders ,  Matthias Schobinger ,  Edoardo Prete ,  Norbert Neurohr ,  Johannes Sturm ,  Eva Tatschl-Unterberger ,  Nicola Dadalt ,  Daniele Gardellini

IPC分类号： H03D3/24

CPC分类号： H04L7/0058

摘要： A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.

摘要翻译： 一种接收数据的方法包括对数据采样点的数据进行采样，以获取与数据中包含的信息相对应的数据采样，并在数据采样点之间的中间采样点采样数据，以获得中间样本。 取决于在至少一个中间采样点之前的数据采样点采样的先前数据采样点和在数据采样中采样的先前中间采样点之间的至少一个数据样本，在中间采样点的至少一个中间采样点处对数据进行校正 在所述至少一个中间采样点之前。

公开(公告)号：US20060029172A1

公开(公告)日：2006-02-09

申请号：US11194494

申请日：2005-08-01

申请人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

发明人： Claudio Andreotti ,  Edoardo Prete ,  Anthony Sanders

IPC分类号： H04L7/00

CPC分类号： H03K5/13 ,  H03K2005/00286 ,  H04L7/0025

摘要： Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s′, c′) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

摘要翻译： 用于产生具有来自多个输入时钟信号的可调相位关系的输出时钟信号的方法和装置。 提供了一种用于产生输出时钟信号（o）的方法和装置，其中具有彼此具有预定相位关系的多个输入时钟信号（s，c）以相应的加权因子（A，1） -A），并且其中加上加权输入时钟信号（s'，c'），以便产生加法时钟信号（i）。 累加时钟信号（i）被积分在积分器（8）中并且可选地被放大以产生输出时钟信号（o）。 具有可调相位关系的输出时钟信号（o）可以通过这样一种方式产生，其中对输入时钟信号的要求不那么严格。

公开(公告)号：US08760946B2

公开(公告)日：2014-06-24

申请号：US13477642

申请日：2012-05-22

申请人： Glenn A Dearth ,  Warren R Anderson ,  Anwar P Kashem ,  Richard W Reeves ,  Edoardo Prete ,  Gerald R Talbot

发明人： Glenn A Dearth ,  Warren R Anderson ,  Anwar P Kashem ,  Richard W Reeves ,  Edoardo Prete ,  Gerald R Talbot

IPC分类号： G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

摘要： Various method and apparatus embodiments for training a delay for enabling a data strobe signal in a memory subsystem are disclosed. In one embodiment, a system includes a memory controller configured to receive a data strobe signal. The memory controller includes a training circuit. The training circuit includes a first storage circuit coupled to receive the data strobe signal on a data input and an enable signal on a clock input, and a training unit configured to, based on an output signal received from the first flip-flop, adjust a phase of the enable signal until an assertion of the enable signal coincides with a preamble indication in the data strobe signal.

摘要翻译： 公开了用于训练用于在存储器子系统中启用数据选通信号的延迟的各种方法和装置实施例。 在一个实施例中，系统包括被配置为接收数据选通信号的存储器控​​制器。 存储器控制器包括训练电路。 训练电路包括：第一存储电路，被耦合以在数据输入端接收数据选通信号;以及训练单元，被配置为基于从第一触发器接收到的输出信号调整一个 使能信号的相位直到使能信号的断言与数据选通信号中的前导码指示一致。

公开(公告)号：US20130136195A1

公开(公告)日：2013-05-30

申请号：US13306680

申请日：2011-11-29

申请人： Aaron Nygren ,  Anwar Kashem ,  Edoardo Prete ,  Gerry Talbot

发明人： Aaron Nygren ,  Anwar Kashem ,  Edoardo Prete ,  Gerry Talbot

IPC分类号： H04L27/00

CPC分类号： G06F13/4243

摘要： A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.

摘要翻译： 公开了第一设备和第二设备之间的数据通信的系统和方法。 该方法包括在第一设备处产生第一时钟信号并产生具有与第一时钟信号相位偏移的第二时钟信号。 时钟信号从第一设备发送到第二设备。 该方法还包括利用第一时钟信号来调节从第二设备发送到第一设备的读选通信号的传输。 该方法还包括利用第二时钟信号调节从第二设备发送到第一设备的数据传送信号的传输。