METHOD FOR FORMING SELF ALIGNED CONTACTS FOR INTEGRATED CIRCUIT DEVICES
    11.
    发明申请
    METHOD FOR FORMING SELF ALIGNED CONTACTS FOR INTEGRATED CIRCUIT DEVICES 有权
    用于形成用于集成电路设备的自对准接触的方法

    公开(公告)号:US20080153294A1

    公开(公告)日:2008-06-26

    申请号:US11697287

    申请日:2007-04-05

    IPC分类号: H01L21/3065

    摘要: A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures. Each of the chips has conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures. The method then applies a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass. A step of cleaning the exposed portion of silicon nitride using an isotropic component is also included. The method forms a second silicon nitride layer on the exposed portion of the second silicon nitride layer and removes the second silicon nitride layer and exposed portion of the first silicon nitride layer to expose the contract region on the substrate. The method processes the exposed contact region using a soft etching technique.

    摘要翻译: 一种用于处理集成电路器件的方法,包括形成自对准接触区域。 该方法包括提供部分完成的半导体晶片,晶片包括一个或多个半导体芯片,其中每个芯片包括多个MOS栅极结构。 栅极结构中的每一个形成在衬底上,并且具有形成在栅极结构之间的接触区域的覆盖部分的第一氮化硅层。 每个芯片具有覆盖氮化硅层和栅极结构的预定厚度的掺杂硅玻璃的保形层。 然后,该方法对掺杂的硅玻璃施加等离子体蚀刻工艺,以使用各向异性蚀刻部件暴露第一氮化硅层的一部分,以垂直去除掺杂的硅玻璃的部分。 还包括使用各向同性组分清洁氮化硅的暴露部分的步骤。 该方法在第二氮化硅层的暴露部分上形成第二氮化硅层,并且去除第二氮化硅层和第一氮化硅层的暴露部分以暴露衬底上的合约区域。 该方法使用软蚀刻技术处理曝光的接触区域。

    CMOS image sensor
    12.
    发明申请
    CMOS image sensor 审中-公开
    CMOS图像传感器

    公开(公告)号:US20060108613A1

    公开(公告)日:2006-05-25

    申请号:US11166639

    申请日:2005-06-24

    IPC分类号: H01L27/148

    CPC分类号: H01L27/14603 H01L27/14601

    摘要: Provided is a CMOS image sensor including a pinned photodiode and a transfer transistor. The CMOS image sensor includes: a substrate; a gate electrode disposed on the substrate and electrically isolated from the substrate by a gate insulating layer; a first floating region disposed in the substrate of one side of the gate electrode; a first impurity region for a photodiode disposed in the substrate of the other side of the gate electrode; a second floating region disposed in the substrate between the first impurity region for the photodiode and the gate electrode; and a second impurity region for the photodiode disposed in a surface portion of the substrate including the first impurity region for the photodiode and the second floating region.

    摘要翻译: 提供了包括钉扎光电二极管和转移晶体管的CMOS图像传感器。 CMOS图像传感器包括:基板; 栅电极,设置在所述基板上,并通过栅极绝缘层与所述基板电隔离; 设置在所述栅电极的一侧的基板中的第一浮置区域; 用于设置在栅极电极的另一侧的基板中的光电二极管的第一杂质区域; 布置在所述基板中的用于所述光电二极管的所述第一杂质区域和所述栅电极之间的第二浮置区域; 以及用于光电二极管的第二杂质区域,设置在包括用于光电二极管的第一杂质区域和第二浮动区域的基板的表面部分中。

    NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same
    13.
    发明申请
    NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same 有权
    NMOS器件,PMOS器件和SOI衬底上形成的SiGe HBT器件及其制造方法

    公开(公告)号:US20050139921A1

    公开(公告)日:2005-06-30

    申请号:US11019179

    申请日:2004-12-23

    摘要: Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

    摘要翻译: 提供了在SOI衬底上实现的NMOS器件,PMOS器件和SiGe HBT器件及其制造方法。 在制造Si基高速器件时,SiGe HBT和CMOS安装在单个SOI衬底上。 特别地,CMOS的源极和漏极由SiGe和金属形成,因此防止漏电流并实现低功耗。 此外,芯片中的发热被抑制,即使在低电压下也可以获得宽的工作范围。

    Optoelectronic device having dual-structural nano dot and method for manufacturing the same
    14.
    发明申请
    Optoelectronic device having dual-structural nano dot and method for manufacturing the same 有权
    具有双结构纳米点的光电器件及其制造方法

    公开(公告)号:US20050006636A1

    公开(公告)日:2005-01-13

    申请号:US10912614

    申请日:2004-08-04

    摘要: An optoelectronic device and a method of manufacturing the same which the optoelectronic effect such as light emission or light reception can be increased by forming a dual-structural nano dot to enhance the confinement density of electrons and holes are provided. The optoelectronic device comprises an electron injection layer, a nano dot, and a hole injection layer. The nano dot has a dual structure composed of an external nano dot and an internal dot. The method of manufacturing the optoelectronic device comprises the steps of forming an electron injection layer on a semiconductor substrate; growing nano dot layer on the electron injection layer by an epi-growth method; heating the nano dot layer so that the nano dot has a dual structure composed of an external nano dot and an internal nano dot; and forming a hole injection layer on the overall structure.

    摘要翻译: 提供了通过形成双结构纳米点以增强电子和空穴的限制密度来提高光发射或光接收等光电效应的光电子器件及其制造方法。 光电子器件包括电子注入层,纳米点和空穴注入层。 纳米点具有由外部纳米点和内部点组成的双重结构。 制造光电器件的方法包括以下步骤:在半导体衬底上形成电子注入层; 通过外延生长法在电子注入层上生长纳米点层; 加热纳米点层,使得纳米点具有由外部纳米点和内部纳米点组成的双重结构; 并在整个结构上形成空穴注入层。

    AUTOMATIC CALIBRATION OF FOURIER-DOMAIN OPTICAL COHERENCE TOMOGRAPHY SYSTEMS
    15.
    发明申请
    AUTOMATIC CALIBRATION OF FOURIER-DOMAIN OPTICAL COHERENCE TOMOGRAPHY SYSTEMS 有权
    FOURIER-DOMAIN光学相干系统的自动校准

    公开(公告)号:US20130128267A1

    公开(公告)日:2013-05-23

    申请号:US13813611

    申请日:2011-08-02

    IPC分类号: G01B9/02

    摘要: A method for calibrating a Fourier domain optical coherence tomography system includes receiving spectral data from an optical detector comprising a linear array of detector elements, each detector element having a position labeled n, wherein detected light was wavelength-dispersed across the linear array of detector elements; determining parameters of a preselected functional relationship between wave number, kn, corresponding to detector element n as a function of optical detector element n based on the spectral data; further receiving subsequent spectral data subsequent to the first-mentioned receiving, wherein detected light was wavelength-dispersed across the linear array of detector elements; converting the subsequent spectral data using the preselected functional relationship between wave number kn and optical detector element n to obtain converted spectral data; and performing an inverse Fourier transform of the converted spectral data to obtain a depth profile.

    摘要翻译: 用于校准傅立叶域光学相干断层摄影系统的方法包括从包括检测器元件的线性阵列的光学检测器接收光谱数据,每个检测器元件具有标记为n的位置,其中检测到的光被波长分散在检测器元件的线性阵列 ; 基于光谱数据确定与检测器元件n相对应的波数kn的预选功能关系的参数作为光检测器元件n的函数; 进一步接收在所述第一次接收之后的随后的光谱数据,其中检测的光被波长分散在检测器元件的线性阵列上; 使用波数kn和光检测器元件n之间的预选功能关系来转换随后的光谱数据,以获得转换的光谱数据; 并对所转换的光谱数据执行逆傅立叶变换以获得深度分布。

    Automatic gain control feedback amplifier
    16.
    发明申请
    Automatic gain control feedback amplifier 有权
    自动增益控制反馈放大器

    公开(公告)号:US20060028279A1

    公开(公告)日:2006-02-09

    申请号:US10995033

    申请日:2004-11-23

    IPC分类号: H03F3/08

    摘要: There is provided a feedback amplifier capable of easily controlling its dynamic range without a separate gain control signal generation circuit. The feedback amplifier includes an input terminal detecting an input voltage from input current, a feedback amplification unit amplifying the input voltage to generate an output signal, and an output terminal outputting a signal amplified by the feedback amplification unit. The feedback amplification unit includes a feedback circuit unit including a feedback resistor located between the input terminal and the output terminal, and a feedback transistor connected in parallel to the feedback resistor; and a bias circuit unit supplying a predetermined bias voltage to the feedback transistor of the feedback circuit unit and merged in the feedback amplification unit.

    摘要翻译: 提供了一种反馈放大器,其能够在没有单独的增益控制信号产生电路的情况下容易地控制其动态范围。 反馈放大器包括检测来自输入电流的输入电压的输入端子,放大输入电压以产生输出信号的反馈放大单元以及输出由反馈放大单元放大的信号的输出端子。 反馈放大单元包括反馈电路单元,该反馈电路单元包括位于输入端子和输出端子之间的反馈电阻器和与反馈电阻器并联连接的反馈晶体管; 以及偏置电路单元,向反馈电路单元的反馈晶体管提供预定的偏置电压并且合并在反馈放大单元中。

    Bipolar transistor, BiCMOS device, and method for fabricating thereof
    17.
    发明申请
    Bipolar transistor, BiCMOS device, and method for fabricating thereof 审中-公开
    双极晶体管,BiCMOS器件及其制造方法

    公开(公告)号:US20050104127A1

    公开(公告)日:2005-05-19

    申请号:US10872593

    申请日:2004-06-22

    CPC分类号: H01L29/7378 H01L21/84

    摘要: Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT is removed and a collector plug disposed at a lateral side of the collector is approached to a base when fabricating a Si-based very high-speed device, whereby it is possible to fabricate the SiGe HBT and an SOI CMOS on a single substrate, reduce the size of the device and the number of masks to be used, and implement the device of high density, low power consumption, and wideband performance.

    摘要翻译: 提供了双极晶体管,BiCMOS器件及其制造方法,其中去除了设置在SiGe HBT的集电极下方的现有子集电极,并且设置在集电极的横向侧的集电极端子在制造时 基于Si的非常高速的器件,由此可以在单个衬底上制造SiGe HBT和SOI CMOS,减少器件的尺寸和使用的掩模的数量,并实现高密度的器件, 低功耗,宽带性能。

    Automatic calibration of fourier-domain optical coherence tomography systems
    18.
    发明授权
    Automatic calibration of fourier-domain optical coherence tomography systems 有权
    傅立叶光学相干断层扫描系统的自动校准

    公开(公告)号:US08921767B2

    公开(公告)日:2014-12-30

    申请号:US13813611

    申请日:2011-08-02

    摘要: A method for calibrating a Fourier domain optical coherence tomography system includes receiving spectral data from an optical detector comprising a linear array of detector elements, each detector element having a position labeled n, wherein detected light was wavelength-dispersed across the linear array of detector elements; determining parameters of a preselected functional relationship between wave number, kn, corresponding to detector element n as a function of optical detector element n based on the spectral data; further receiving subsequent spectral data subsequent to the first-mentioned receiving, wherein detected light was wavelength-dispersed across the linear array of detector elements; converting the subsequent spectral data using the preselected functional relationship between wave number kn and optical detector element n to obtain converted spectral data; and performing an inverse Fourier transform of the converted spectral data to obtain a depth profile.

    摘要翻译: 用于校准傅立叶域光学相干断层摄影系统的方法包括从包括检测器元件的线性阵列的光学检测器接收光谱数据,每个检测器元件具有标记为n的位置,其中检测到的光被波长分散在检测器元件的线性阵列 ; 基于光谱数据确定与检测器元件n相对应的波数kn的预选功能关系的参数作为光检测器元件n的函数; 进一步接收在所述第一次接收之后的随后的光谱数据,其中检测的光被波长分散在检测器元件的线性阵列上; 使用波数kn和光检测器元件n之间的预选功能关系来转换随后的光谱数据,以获得转换的光谱数据; 并对所转换的光谱数据执行逆傅立叶变换以获得深度分布。

    Method for forming self aligned contacts for integrated circuit devices
    20.
    发明授权
    Method for forming self aligned contacts for integrated circuit devices 有权
    用于形成用于集成电路器件的自对准触点的方法

    公开(公告)号:US07928000B2

    公开(公告)日:2011-04-19

    申请号:US11697287

    申请日:2007-04-05

    IPC分类号: H01L21/4763

    摘要: A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures. Each of the chips has conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures. The method then applies a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass. A step of cleaning the exposed portion of silicon nitride using an isotropic component is also included. The method forms a second silicon nitride layer on the exposed portion of the second silicon nitride layer and removes the second silicon nitride layer and exposed portion of the first silicon nitride layer to expose the contract region on the substrate. The method processes the exposed contact region using a soft etching technique.

    摘要翻译: 一种用于处理集成电路器件的方法,包括形成自对准接触区域。 该方法包括提供部分完成的半导体晶片,晶片包括一个或多个半导体芯片,其中每个芯片包括多个MOS栅极结构。 栅极结构中的每一个形成在衬底上,并且具有形成在栅极结构之间的接触区域的覆盖部分的第一氮化硅层。 每个芯片具有覆盖氮化硅层和栅极结构的预定厚度的掺杂硅玻璃的保形层。 然后,该方法对掺杂的硅玻璃施加等离子体蚀刻工艺,以使用各向异性蚀刻部件暴露第一氮化硅层的一部分,以垂直去除掺杂的硅玻璃的部分。 还包括使用各向同性组分清洁氮化硅的暴露部分的步骤。 该方法在第二氮化硅层的暴露部分上形成第二氮化硅层,并且去除第二氮化硅层和第一氮化硅层的暴露部分以暴露衬底上的合约区域。 该方法使用软蚀刻技术处理曝光的接触区域。