公开(公告)号：US11513894B2

公开(公告)日：2022-11-29

申请号：US17135722

申请日：2020-12-28

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Amir Nassie ,  Anat Rot ,  Ofir Kanter ,  Hanan Weingarten

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/29

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

公开(公告)号：US11183259B2

公开(公告)日：2021-11-23

申请号：US16866483

申请日：2020-05-04

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Hanan Weingarten ,  Yasuhiko Kurosawa

IPC: G11C29/02 ,  G11C16/34 ,  G11C16/04

Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.

公开(公告)号：US20250007537A1

公开(公告)日：2025-01-02

申请号：US18887114

申请日：2024-09-17

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Zion Nahisi ,  Ofir Kanter ,  Amir Nassie ,  Hanan Weingarten

IPC: H03M13/29 ,  H03M13/11 ,  H03M13/15 ,  H03M13/45

Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

公开(公告)号：US20240312528A1

公开(公告)日：2024-09-19

申请号：US18122758

申请日：2023-03-17

Applicant: Kioxia Corporation

Inventor： Eyal Nitzan ,  Avi Steiner ,  Hanan Weingarten

IPC: G11C16/26 ,  G11C11/54 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/54 ,  G11C16/349

Abstract: A method for reading data from a solid-state drive (SSD) configured to store data in a plurality of memory cells arranged in memory blocks comprising rows, the method performed by a controller in communication with the plurality of memory cells. The method comprises retrieving data from a target row of memory cells of the plurality of memory cells associated with a read request received from a host using initial threshold voltages. The method also includes decoding the data using a hard decision stage. Additionally the method comprises estimating read threshold voltages of the target row of memory cells based on a transformation of a distribution of threshold voltages of cells in a memory block containing the target row when the hard decision decoding stage fails. The method further includes retrieving data from the target row using the estimated read threshold voltages.

公开(公告)号：US12095481B2

公开(公告)日：2024-09-17

申请号：US17586290

申请日：2022-01-27

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Zion Nahisi ,  Ofir Kanter ,  Amir Nassie ,  Hanan Weingarten

IPC: H03M13/29 ,  H03M13/11 ,  H03M13/15 ,  H03M13/45

CPC classification number: H03M13/2909 ,  H03M13/1108 ,  H03M13/1125 ,  H03M13/1128 ,  H03M13/152 ,  H03M13/458

Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

公开(公告)号：US11923025B2

公开(公告)日：2024-03-05

申请号：US17131509

申请日：2020-12-22

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Hanan Weingarten ,  Yasuhiko Kurosawa ,  Neil Buxton

IPC: G11C29/42 ,  G11C16/10 ,  G11C16/26 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C16/10 ,  G11C16/26 ,  G11C29/44

Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.

公开(公告)号：US20230336190A1

公开(公告)日：2023-10-19

申请号：US18341041

申请日：2023-06-26

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner ,  Amir Nassie ,  Hanan Weingarten

IPC: H03M13/29 ,  H03M13/11

CPC classification number: H03M13/118 ,  H03M13/2909

Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

公开(公告)号：US20230221879A1

公开(公告)日：2023-07-13

申请号：US17574929

申请日：2022-01-13

Applicant: Kioxia Corporation

Inventor： Hanan Weingarten

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage. The circuit may be configured to determine a second reference voltage based on the first soft read sample. The circuit may be configured to obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage. The circuit may be configured to generate soft information based on the first and second soft read samples. The circuit may be configured to decode a result of a third read operation on the location of the flash memory based on the soft information.

公开(公告)号：US11689219B1

公开(公告)日：2023-06-27

申请号：US17401215

申请日：2021-08-12

Applicant: Kioxia Corporation

Inventor： Ofir Kanter ,  Avi Steiner ,  Amir Nassie ,  Hanan Weingarten

IPC: H03M13/11 ,  H03M13/29

CPC classification number: H03M13/118 ,  H03M13/2909

Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

公开(公告)号：US20220209791A1

公开(公告)日：2022-06-30

申请号：US17135722

申请日：2020-12-28

Applicant: Kioxia Corporation

Inventor： Avi Steiner ,  Amir Nassie ,  Anat Rot ,  Ofir Kanter ,  Hanan Weingarten

IPC: H03M13/11

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.