公开(公告)号：US20050185466A1

公开(公告)日：2005-08-25

申请号：US10785785

申请日：2004-02-24

申请人： Kirk Prall

发明人： Kirk Prall

IPC分类号： H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L29/7887 ,  H01L29/7923

摘要： A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

摘要翻译： 多态NAND存储单元由衬底中的两个漏极/源极区域组成。 在漏极/源极区域之间的衬底上方形成氧化物 - 氮化物 - 氧化物结构。 用作不对称电荷捕获层的氮化物层。 控制栅极位于氧化物 - 氮化物 - 氧化物结构之上。 在漏极/源极区域上的不对称偏置导致具有较高电压的漏极/源极区域通过栅极感应漏极漏极注入到基本上邻近该漏极/源极区域的捕获层而注入不对称分布孔。

公开(公告)号：US06255693B1

公开(公告)日：2001-07-03

申请号：US09259790

申请日：1999-03-01

申请人： Kirk Prall ,  Alan R. Reinberg

发明人： Kirk Prall ,  Alan R. Reinberg

IPC分类号： H01L2701

CPC分类号： H01L27/10873 ,  H01J37/3171 ,  H01L21/26513 ,  H01L29/10 ,  H01L29/105 ,  H01L29/36

摘要： A method and apparatus for performing multiple implantations in a semiconductor wafer is used to set variable implantation waveforms. An implanter is used, which allows for setting of variable waveforms, corresponding to energy, beam current, and angle, used for implantation. At least one of a ramping voltage, a ramping beam current source, and a programmable motor mechanically connected to a wafer table is used to obtain the variable waveforms. Using the implanter and method of the invention, detailed doping profiles are created using only a single implant. Such detailed doping profiles are used to create high gradient retrograde wells, and transistors with punch-through suppression implants and channel implants with controlled dopant gradients.

摘要翻译： 用于在半导体晶片中进行多次注入的方法和装置用于设置可变注入波形。 使用一个注入机，它可以设置对应于用于植入的能量，束流和角度的可变波形。 使用斜坡电压，斜波束电流源和机械地连接到晶片台的可编程电机中的至少一个来获得可变波形。 使用本发明的注入机和方法，仅使用单个植入物产生详细的掺杂分布。 这种详细的掺杂分布用于创建高梯度逆行阱，以及具有穿通抑制植入物和具有受控掺杂剂梯度的通道植入物的晶体管。

公开(公告)号：US06255209B1

公开(公告)日：2001-07-03

申请号：US09376023

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.

摘要翻译： 提供了通过化学气相沉积（CVD）在集成电路中形成接触的方法。 所述方法包括在接触中形成钛。 一种方法包括通过在氢气存在下将钛前体组合而形成钛。 另一种方法包括在氢的存在下将四氯化钛，TiCl 4组合形成钛。 另一种方法包括在氢的存在下，通过组合四（二甲基氨基）钛，Ti（N（CH 3）2）4形成钛。

公开(公告)号：US06208033B1

公开(公告)日：2001-03-27

申请号：US09377253

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： Apparatus having titanium silicide and titanium formed by chemical vapor deposition (CVD) in a contact. The chemical vapor deposition includes forming titanium silicide and/or titanium by combining a titanium precursor in the presence of hydrogen, H2. The chemical vapor deposition may further include forming titanium silicide and/or titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. The chemical vapor deposition may further include forming titanium silicide and/or by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. For production of titanium silicide, reaction of the titanium precursor may occur with a silicon precursor or a silicon source occurring as part of the contact. Use of a silicon precursor reduces depletion of a silicon base layer in the contact.

摘要翻译： 具有通过化学气相沉积（CVD）在接触中形成的钛硅化物和钛的装置。 化学气相沉积包括通过在氢气存在下将钛前体组合而形成钛硅化物和/或钛。 化学气相沉积还可以包括在氢的存在下通过组合四氯化钛TiCl 4来形成硅化钛和/或钛。 化学气相沉积可以进一步包括在氢的存在下形成硅化钛和/或通过组合四（二甲基氨基）钛（N（CH 3）2）4）。 对于硅化钛的生产，钛前体的反应可以与作为接触部分的硅前体或硅源发生。 硅前体的使用减少了接触中硅基层的耗尽。

公开(公告)号：US6160277A

公开(公告)日：2000-12-12

申请号：US273080

申请日：1999-03-19

申请人： Kirk Prall

发明人： Kirk Prall

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L21/76831 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628

摘要： A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expense of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in place, etching the first gate block selectively relative to the insulating dielectric layer to define the transistor gate having a second lateral expanse adjacent the substrate which is equal to the resultant lateral expanse; and g) providing a conductivity enhancing impurity into the substrate adjacent the transistor gate. The invention has particular utility in fabrication of field effect transistors having an elevated source and an elevated drain. The invention also contemplates products produced by the above process.

摘要翻译： 一种形成相对于半导体衬底的场效应晶体管的方法，其中所述晶体管具有限定用于提供晶体管沟道区的半导体材料的合成横向费用的栅极，其包括：a）在半导体衬底上提供导电栅极层 ; b）将所述导电栅层图案化成第一栅极块，所述第一栅极块具有大于所产生的横向扩展的第一横向延伸; c）在所述第一栅极块上提供绝缘介电层; d）在第一栅极块和绝缘电介质层上提供光致抗蚀剂的图案化层，所述图案化光致抗蚀剂包括位于第一栅极块的第一横向扩展部之上和之内的光致抗蚀剂阻挡层; e）使图案化的光致抗蚀剂在适当位置，相对于第一栅极块选择性地蚀刻绝缘介电层; f）在蚀刻绝缘电介质层和图案化的光致抗蚀剂就位之后，相对于绝缘电介质层选择性地蚀刻第一栅极块以限定晶体管栅极，其具有与基板相邻的第二横向宽度，其等于所得到的横向宽度; 和g）在与晶体管栅极相邻的衬底中提供增强电导率的杂质。 本发明在具有升高的源极和升高的漏极的场效应晶体管的制造中具有特别的用途。 本发明还考虑了通过上述方法生产的产品。

公开(公告)号：US6080675A

公开(公告)日：2000-06-27

申请号：US344435

申请日：1999-06-25

申请人： Kirk Prall ,  Guy Blalock

发明人： Kirk Prall ,  Guy Blalock

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/02043 ,  Y02P80/30 ,  Y10S438/906 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.

摘要翻译： 一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。 在本发明的方法中，在用于制造晶片上的部件的工艺的正常涂覆步骤中，在前侧上沉积蜂窝层。 覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。 通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。 在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。 由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

公开(公告)号：US6057200A

公开(公告)日：2000-05-02

申请号：US831360

申请日：1997-04-01

申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

摘要翻译： 一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底 不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，和ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

公开(公告)号：US5958796A

公开(公告)日：1999-09-28

申请号：US915193

申请日：1997-08-20

申请人： Kirk Prall ,  Guy Blalock

发明人： Kirk Prall ,  Guy Blalock

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L21/02043 ,  Y02P80/30 ,  Y10S438/906 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer. Since the cover layer is deposited in a normal coating step of the process for fabricating a component on the wafer, it is deposited irrespective of whether the waste matter is removed from the wafer.

摘要翻译： 一种在晶片上制造半导体器件的方法，该半导体器件具有正面和背面的衬底，以及在衬底的背面积聚废物。 在本发明的方法中，在用于在晶片上制造部件的工艺的正常涂覆步骤中，在正面上沉积覆盖层。 覆盖层提供用于制造晶片正面上的部件的工艺中使用的材料，并在前侧形成阻挡层。 通过用合适的蚀刻剂从晶片的背面蚀刻废物，或者通过化学机械平坦化（“CMP”）工艺平坦化晶片的背面，从晶片的背面去除废物。 在去除步骤期间，覆盖层保护前侧，并且当废物从晶片的背面移除时，前侧上的任何装置特征不被损坏。 由于覆盖层在用于制造晶片上的部件的工艺的正常涂覆步骤中沉积，所以不管废物是否从晶片上移除，都被沉积。

公开(公告)号：US5858865A

公开(公告)日：1999-01-12

申请号：US569838

申请日：1995-12-07

申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/3205

CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978

摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。

公开(公告)号：US5759905A

公开(公告)日：1998-06-02

申请号：US956918

申请日：1997-10-23

申请人： Pai-Hung Pan ,  Sujit Sharan ,  Kirk Prall

发明人： Pai-Hung Pan ,  Sujit Sharan ,  Kirk Prall

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76877

摘要： A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 ; e) after increasing the dopant concentration of the first layer, providing a second layer of semiconductive material over the first layer and to within the first remaining opening, the second layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; f) after providing the second layer within the first remaining opening, increasing the average conductivity enhancing dopant concentration of the second layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 ; and g) providing the contact opening to be substantially filled with semiconductive material having an average conductivity enhancing dopant concentration of greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 to define a conductively doped semiconductive material plug within the contact opening.