公开(公告)号：US20080309481A1

公开(公告)日：2008-12-18

申请号：US12155457

申请日：2008-06-04

申请人： Takeshi Tanaka ,  Shunzo Yamashita ,  Kiyoshi Aiki

发明人： Takeshi Tanaka ,  Shunzo Yamashita ,  Kiyoshi Aiki

IPC分类号： H04Q7/00

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/11 ,  A61B5/7232 ,  A61B2560/045 ,  A61B2562/0219 ,  H04W84/18

摘要： Provided is a sensor node including: a sensor for measuring biological information; a CPU for acquiring data by driving the sensor; a wireless communication unit for transmitting the data acquired by the CPU; a battery for supplying the control unit, the wireless communication unit, and the sensor with electric power; a RAM for storing the data; a compression unit for compressing the data stored in the RAM when the wireless communication unit cannot carry out the transmission; and a flash memory for storing the compressed data, thereby storing as much sensing data as possible on the sensor node, which is limited in resources, and preventing loss of the sensing data.

摘要翻译： 提供了一种传感器节点，包括：用于测量生物信息的传感器; 用于通过驱动传感器来获取数据的CPU; 用于发送由CPU获取的数据的无线通信单元; 用于向控制单元，无线通信单元和传感器供电的电池; 用于存储数据的RAM; 压缩单元，用于在无线通信单元不能进行发送时压缩存储在RAM中的数据; 以及用于存储压缩数据的闪速存储器，从而在传感器节点上存储尽可能多的感测数据，其在资源上受到限制，并且防止感测数据的丢失。

公开(公告)号：US5710770A

公开(公告)日：1998-01-20

申请号：US462532

申请日：1995-06-05

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US5410540A

公开(公告)日：1995-04-25

申请号：US132999

申请日：1993-10-07

申请人： Kiyoshi Aiki ,  Takahiko Kozaki ,  Noboru Endo ,  Haruo Shibata

发明人： Kiyoshi Aiki ,  Takahiko Kozaki ,  Noboru Endo ,  Haruo Shibata

IPC分类号： H04Q3/52 ,  H04L12/18 ,  H04L12/931 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/309 ,  H04L2012/5672

摘要： In a shared-buffer-type ATM switch including a multiplexer, a shared buffer memory, a demultiplexer, a buffer memory controller, a cell copy section is disposed between the multiplexer and the memory. The copy section produces a plurality of copies of a broadcast cell according to information of a copy information table and adds associate routing information to each copied cell so as to write the cells in the memory. In response to an indication from an output counter, the cells are read from the memory to be distributed to output ports, thereby implementing a broadcast function.

摘要翻译： 在包括多路复用器，共享缓冲存储器，解复用器，缓冲存储器控制器的共享缓冲器型ATM交换机中，单元复制部分设置在多路复用器和存储器之间。 复制部分根据复制信息表的信息产生广播小区的多个副本，并将关联路由信息添加到每个复制的小区，以便将单元写入存储器。 响应于来自输出计数器的指示，从存储器读取单元以分配到输出端口，从而实现广播功能。

公开(公告)号：US07696867B2

公开(公告)日：2010-04-13

申请号：US11779020

申请日：2007-07-17

申请人： Kiyoshi Aiki ,  Shunzo Yamashita ,  Takeshi Tanaka

发明人： Kiyoshi Aiki ,  Shunzo Yamashita ,  Takeshi Tanaka

IPC分类号： G08B1/08 ,  G08B21/00 ,  G06F1/26 ,  G06F1/00

CPC分类号： H04W52/029 ,  H04W84/18 ,  H04W88/02

摘要： A sensor node for intermittently sensing data in a short cycle includes a control unit for acquiring information by driving the sensor, a radio communication unit for transmitting the information acquired by the control unit and a battery for supplying the control unit. The control unit includes a clock supply unit (RTC) for supplying the control unit with clocks at a predetermined frequency. A sensor control unit starts the supply of power to the sensor when the measurement period has begun, maintains the power supply to the sensor even if the control unit has shifted to the standby state during the measurement period, and shuts down the power supply to the sensor when the measurement period has been completed. A measurement unit is also provided for acquiring information from the sensor every time the latter has shifted to the operational state.

摘要翻译： 用于在短周期内间歇地感测数据的传感器节点包括用于通过驱动传感器获取信息的控制单元，用于发送由控制单元获取的信息的无线电通信单元和用于提供控制单元的电池。 控制单元包括用于向控制单元提供预定频率的时钟的时钟提供单元（RTC）。 当测量周期已经开始时，传感器控制单元开始向传感器供电，即使控制单元在测量期间已经转移到待机状态，也保持对传感器的供电，并且关闭到 传感器，当测量周期已经完成。 还提供测量单元，用于每当后者转移到操作状态时从传感器获取信息。

公开(公告)号：US20080055069A1

公开(公告)日：2008-03-06

申请号：US11779020

申请日：2007-07-17

申请人： Kiyoshi Aiki ,  Shunzo Yamashita ,  Takeshi Tanaka

发明人： Kiyoshi Aiki ,  Shunzo Yamashita ,  Takeshi Tanaka

IPC分类号： H04Q7/00 ,  G08B1/08

CPC分类号： H04W52/029 ,  H04W84/18 ,  H04W88/02

摘要： A sensor node for intermittently sensing data in a short cycle includes a control unit for acquiring information by driving the sensor, a radio communication unit for transmitting the information acquired by the control unit and a battery for supplying the control unit. The control unit includes a clock supply unit (RTC) for supplying the control unit with clocks at a predetermined frequency. A sensor control unit starts the supply of power to the sensor when the measurement period has begun, maintains the power supply to the sensor even if the control unit has shifted to the standby state during the measurement period, and shuts down the power supply to the sensor when the measurement period has been completed. A measurement unit is also provided for acquiring information from the sensor every time the latter has shifted to the operational state.

摘要翻译： 用于在短周期内间歇地感测数据的传感器节点包括用于通过驱动传感器获取信息的控制单元，用于发送由控制单元获取的信息的无线电通信单元和用于提供控制单元的电池。 控制单元包括用于向控制单元提供预定频率的时钟的时钟提供单元（RTC）。 当测量周期已经开始时，传感器控制单元开始向传感器供电，即使控制单元在测量期间已经转移到待机状态，也保持对传感器的供电，并且关闭到 传感器，当测量周期已经完成。 还提供测量单元，用于每当后者转移到操作状态时从传感器获取信息。

公开(公告)号：US20070191719A1

公开(公告)日：2007-08-16

申请号：US11723930

申请日：2007-03-22

申请人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

发明人： Shunzo Yamashita ,  Hiroyuki Kuriyama ,  Kiyoshi Aiki ,  Takanori Shimura

IPC分类号： A61B5/02

CPC分类号： A61B5/0002 ,  A61B5/02438 ,  A61B5/681 ,  A61B2560/0209

摘要： The precision of measuring biometric information is enhanced while suppressing the consumption of a battery in a sensor node. In a method of measuring the biometric information in a sensor node including a controller for driving a sensor to measure biometric information, the controller supplies power from a battery to an acceleration sensor for detecting the movement of a living body to detect the movement of the living body, the controller determines whether or not measurement by a pulsebeat sensor is possible based on the detected movement of the living body (P330), and shuts off power to the acceleration sensor having a power consumption lower than that of the pulsebeat sensor when the determination results show that measurement is possible, and thereafter supplying power to the pulsebeat sensor having a power consumption larger than that of the acceleration sensor to measure the biometric information (P340).

摘要翻译： 在抑制传感器节点中的电池消耗的同时增强了测量生物信息的精度。 在测量包括用于驱动传感器以测量生物特征信息的控制器的传感器节点中的生物信息的方法中，控制器将电力从电池供给到加速度传感器，用于检测活体的运动以检测生物的移动 控制器基于检测到的活体的移动来确定是否可以通过脉搏波传感器进行测量（P 330），并且在功率消耗低于脉冲波形传感器的功率消耗的加速度传感器时切断电力 确定结果表明测量是可能的，然后向具有大于加速度传感器功率消耗的脉冲波形传感器供电以测量生物特征信息（P 340）。

公开(公告)号：US20070030154A1

公开(公告)日：2007-02-08

申请号：US11208632

申请日：2005-08-23

申请人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunjo Yamashita ,  Takanori Shimura

发明人： Kiyoshi Aiki ,  Hiroyuki Kuriyama ,  Shunjo Yamashita ,  Takanori Shimura

IPC分类号： G08B13/14

CPC分类号： H01Q1/273 ,  H01Q9/0485

摘要： To secure a stable radio-communication performance in a sensor node, the sensor node with a radio-communication circuit and a sensor, for transmitting data measured by the sensor through radio-communication, includes a first board BO2 on which an antenna ANT1 connected to the radio-communication circuit is placed, a case CASE1 containing the first board BO2, and a band that is attached to the case CASE1 so as to fix the case CASE1 to the skin. The antenna ANT1 is placed in an upper portion of the case CASE1, which corresponds to a 12 o'clock direction of a wristwatch.

摘要翻译： 为了确保传感器节点中的稳定的无线电通信性能，具有用于通过无线电通信传输由传感器测量的数据的无线电通信电路和传感器的传感器节点包括第一板BO 2，天线ANT 1 连接到无线电通信电路的情况下，包含第一板BO 2的壳体1和附接到壳体1的带，以将壳体1固定到皮肤上。 天线ANT1被放置在壳体1的与手表的12点钟方向对应的上部。

公开(公告)号：US06330240B1

公开(公告)日：2001-12-11

申请号：US09351125

申请日：1999-07-12

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。

公开(公告)号：US06282611B1

公开(公告)日：2001-08-28

申请号：US08446278

申请日：1995-05-22

申请人： Nobuo Hamamoto ,  Minoru Nagata ,  Masatoshi Ohtake ,  Katsutaka Kimura ,  Toshio Sasaki ,  Hiroshi Kishida ,  Isamu Orita ,  Katsuro Sasaki ,  Naoki Ozawa ,  Kazuhiro Kondo ,  Toshiaki Masuhara ,  Tadashi Onishi ,  Hidehito Obayashi ,  Kiyoshi Aiki ,  Hisashi Horikoshi

发明人： Nobuo Hamamoto ,  Minoru Nagata ,  Masatoshi Ohtake ,  Katsutaka Kimura ,  Toshio Sasaki ,  Hiroshi Kishida ,  Isamu Orita ,  Katsuro Sasaki ,  Naoki Ozawa ,  Kazuhiro Kondo ,  Toshiaki Masuhara ,  Tadashi Onishi ,  Hidehito Obayashi ,  Kiyoshi Aiki ,  Hisashi Horikoshi

IPC分类号： G06F1200

CPC分类号： G07F7/1008 ,  G07F17/16 ,  H02J7/0063

摘要： In a digital information system for realizing the sale of information or the like having a commercial value in the form of a digital signal, and an audio processor, and signal processor suitably used with the system, when a digital signal is received/delivered, a digital signal source is connected directly to a player for receiving and storing a specified information, which is reproduced by the player independently. A voice interval of a digital audio signal is processed to realize the slow and fast playback. The system includes a data compressor and a data extender of simple configuration. The value of the digital signal received/delivered can be exhibited directly. A selling system is constructed easily, and the player is simple in configuration and easy to operate by anyone. The fast and slow playback are possible without deteriorating the sound quality, and ripples can be greatly reduced against the digital input signal, thereby making possible a faithful data compression of an acoustic signal or the like by a simple configuration. The self-diagnosis function permits the use of a defective memory chip, thereby leading to a very economical system.

公开(公告)号：US5365519A

公开(公告)日：1994-11-15

申请号：US845668

申请日：1992-03-04

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。