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    Metal-insulator-metal-insulator-metal (MIMIM) memory device
    13.
    发明授权
    Metal-insulator-metal-insulator-metal (MIMIM) memory device 有权
    金属绝缘体 - 金属 - 绝缘体 - 金属（MIMIM）存储器件

    公开(公告)号：US08717803B2

    公开(公告)日：2014-05-06

    申请号：US13316172

    申请日：2011-12-09

    Applicant: Manuj Rathor ,  Suzette K Pangrle ,  Steven Avanzino ,  Zhida Lan

    Inventor： Manuj Rathor ,  Suzette K Pangrle ,  Steven Avanzino ,  Zhida Lan

    IPC: G11C11/00

    CPC classification number: H01L45/10 ,  G11C13/0007 ,  H01L45/146

    Abstract: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

    Abstract translation: 本存储器件包括第一和第二电极，电极之间的第一和第二绝缘层，第一绝缘层与第一电极接触，第二绝缘层与第二电极接触，第一绝缘层与第一电极之间的金属层 和第二绝缘层。 进一步包括在第一绝缘层和金属层之间并与之接触的第一氧化物层，以及在第二绝缘层和金属层之间并与之接触的第二氧化物层。

    Increasing self-aligned contact areas in integrated circuits using a disposable spacer
    15.
    发明授权
    Increasing self-aligned contact areas in integrated circuits using a disposable spacer 有权
    使用一次性间隔件增加集成电路中的自对准接触面积

    公开(公告)号：US07323377B1

    公开(公告)日：2008-01-29

    申请号：US11089732

    申请日：2005-03-25

    Applicant: Mehran Sedigh ,  Manuj Rathor ,  Alain P. Blosse ,  Dutta Saurabh Chowdhury

    Inventor： Mehran Sedigh ,  Manuj Rathor ,  Alain P. Blosse ,  Dutta Saurabh Chowdhury

    IPC: H01L21/336

    CPC classification number: H01L29/6656 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/66575 ,  H01L29/78

    Abstract: In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

    Abstract translation: 在一个实施例中，制造集成电路的方法包括以下步骤：（i）在晶体管栅极的侧壁上形成复合间隔物，每个复合间隔物包括具有台阶部分的第一衬垫和在台阶上的一次性衬垫材料 一部分; （ii）通过在源极/漏极区域上的第一衬垫的一部分进行离子注入来形成源极/漏极区域; （iii）在形成所述源极/漏极区域之后，用形成在所述第一衬里上的第二衬垫替换所述一次性间隔物材料; （iv）在所述第二衬垫上形成预金属电介质; 和（v）通过预金属电介质形成自对准接触。 除了其他优点之外，该方法允许增加自对准接触的接触面积。

    Metal-insulator-metal-insulator-metal (MIMIM) memory device
    17.
    发明授权
    Metal-insulator-metal-insulator-metal (MIMIM) memory device 有权
    金属绝缘体 - 金属 - 绝缘体 - 金属（MIMIM）存储器件

    公开(公告)号：US08093680B1

    公开(公告)日：2012-01-10

    申请号：US11521219

    申请日：2006-09-14

    Applicant: Manuj Rathor ,  Suzette K. Pangrle ,  Steven Avanzino ,  Zhida Lan

    Inventor： Manuj Rathor ,  Suzette K. Pangrle ,  Steven Avanzino ,  Zhida Lan

    IPC: H01L29/68

    CPC classification number: H01L45/10 ,  G11C13/0007 ,  H01L45/146

    Abstract: The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

    Abstract translation: 本存储器件包括第一和第二电极，电极之间的第一和第二绝缘层，第一绝缘层与第一电极接触，第二绝缘层与第二电极接触，第一绝缘层与第一电极之间的金属层 和第二绝缘层。 进一步包括在第一绝缘层和金属层之间并与之接触的第一氧化物层，以及在第二绝缘层和金属层之间并与之接触的第二氧化物层。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION
    20.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION 有权
    形成具有应力通道区域的场效应晶体管的半导体结构的方法

    公开(公告)号：US20080102590A1

    公开(公告)日：2008-05-01

    申请号：US11750816

    申请日：2007-05-18

    Applicant: Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    Inventor： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    IPC: H01L21/336 ,  H01L21/428

    CPC classification number: H01L29/7833 ,  H01L21/268 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

    Abstract translation: 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区，而第二晶体管元件包括至少一个第二非晶区。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，进行第二退火处理。 应力产生层在第二退火工艺期间保留在半导体衬底上。

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