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    Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region
    1.
    发明授权
    Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region 有权
    一种形成半导体结构的方法，包括具有应力沟道区的场效应晶体管

    公开(公告)号：US07772077B2

    公开(公告)日：2010-08-10

    申请号：US11750816

    申请日：2007-05-18

    申请人： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    发明人： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/268 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

    摘要翻译： 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区，而第二晶体管元件包括至少一个第二非晶区。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，进行第二退火处理。 应力产生层在第二退火工艺期间保留在半导体衬底上。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION
    2.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION 有权
    形成具有应力通道区域的场效应晶体管的半导体结构的方法

    公开(公告)号：US20080102590A1

    公开(公告)日：2008-05-01

    申请号：US11750816

    申请日：2007-05-18

    申请人： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    发明人： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

    IPC分类号： H01L21/336 ,  H01L21/428

    CPC分类号： H01L29/7833 ,  H01L21/268 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

    摘要翻译： 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区，而第二晶体管元件包括至少一个第二非晶区。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，进行第二退火处理。 应力产生层在第二退火工艺期间保留在半导体衬底上。

    Plasma etch chemistry and method of improving etch control
    5.
    发明授权
    Plasma etch chemistry and method of improving etch control 失效
    等离子蚀刻化学和改进蚀刻控制的方法

    公开(公告)号：US06372634B1

    公开(公告)日：2002-04-16

    申请号：US09333459

    申请日：1999-06-15

    申请人： Jianmin Qiao ,  Sanjay Thekdi ,  Manuj Rathor ,  James E. Nulty

    发明人： Jianmin Qiao ,  Sanjay Thekdi ,  Manuj Rathor ,  James E. Nulty

    IPC分类号： H01L213065

    CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76816

    摘要： A plasma etch chemistry and etch methodology is provided to improve critical dimension control for openings formed into and/or through a semiconductor thin film. According to an embodiment, the plasma etch chemistry includes an etchant mixture comprising a first etchant of the formula CxHyFz (where x≧2, y≧1 and z≧2) and a second etchant other than the first etchant to form the openings. The relationship of x, y and z may be such that y+z equals an even number ≦2x+2. According to an alternative embodiment, the plasma etch chemistry further includes strained cyclic (hydro)fluorocarbon. The plasma etch chemistry may be used to form openings in the layer in a single-etch step. In a further embodiment, the plasma etch chemistry described herein may etch less than the entire thickness of the layer, and a second plasma etch chemistry substantially free of the first etchant and strained cyclic (hydro)fluorocarbons etches the remainder of the layer to form the openings. Such an etch methodology advantageously reduces the risk of etching the materials underlying the layer.

    摘要翻译： 提供等离子体蚀刻化学和蚀刻方法以改进形成于和/或穿过半导体薄膜的开口的临界尺寸控制。 根据实施例，等离子体蚀刻化学品包括蚀刻剂混合物，其包含式C x H y F z（其中x> = 2，y> = 1和z> = 2）的第一蚀刻剂和除第一蚀刻剂之外的第二蚀刻剂， 开口 x，y和z的关系可以使得y + z等于偶数<= 2x + 2。 根据替代实施例，等离子体蚀刻化学品还包括应变的环状（氢）氟碳化合物。 等离子体蚀刻化学可以用于在单蚀刻步骤中在层中形成开口。 在另一个实施方案中，本文所述的等离子体蚀刻化学蚀刻可以蚀刻小于层的整个厚度，并且基本上不含第一蚀刻剂的第二等离子体蚀刻化学品和应变的环状（氢）氟碳化物蚀刻该层的其余部分，形成 开口 这种蚀刻方法有利地降低了蚀刻层之下的材料的风险。

    Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices
    8.
    发明授权
    Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices 有权
    用于SONOS型器件的氧化物 - 氮化物（ONO）电介质的制造方法

    公开(公告)号：US06969689B1

    公开(公告)日：2005-11-29

    申请号：US10184715

    申请日：2002-06-28

    申请人： Krishnaswamy Ramkumar ,  Manuj Rathor ,  Biju Parameshwaran ,  Loren Lancaster

    发明人： Krishnaswamy Ramkumar ,  Manuj Rathor ,  Biju Parameshwaran ,  Loren Lancaster

    IPC分类号： H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/469 ,  H01L21/8246 ,  H01L27/115

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/115

    摘要： A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

    摘要翻译： 公开了一种形成SONOS型非易失性存储装置的氧化物 - 氧化物 - 氧化物（ONO）电介质的方法。 根据第一实施例，一种方法可以包括以下步骤：形成隧道电介质（步骤102），形成电荷存储电介质（步骤104），以及在相同的晶片处理工具中形成顶部绝缘层（步骤106）。 根据实施例的各个方面，SONOS型器件的ONO电介质的所有层可以形成在相同的一般温度范围内。 此外，隧道电介质可以包括形成有长的低压氧化的隧道氧化物，并且顶部绝缘层可以包括用预热的源气体形成的二氧化硅。